configure.in (skipdirs): Don't build target-libiberty for SPU.
ChangeLog * configure.in (skipdirs) : Don't build target-libiberty for SPU. * configure : Rebuilt. gcc/ChangeLog * config.gcc : Add target for SPU. * config/spu/constraints.md : New file. * config/spu/crt0.c : New file. * config/spu/crtend.c : New file. * config/spu/crti.asm : New file. * config/spu/crtn.asm : New file. * config/spu/float_unsdidf.c : New file. * config/spu/float_unssidf.c : New file. * config/spu/predicates.md : New file. * config/spu/spu-builtins.def : New file. * config/spu/spu-builtins.h : New file. * config/spu/spu-builtins.md : New file. * config/spu/spu-c.c : New file. * config/spu/spu-elf.h : New file. * config/spu/spu-modes.def : New file. * config/spu/spu-protos.h : New file. * config/spu/spu.c : New file. * config/spu/spu.h : New file. * config/spu/spu.md : New file. * config/spu/spu.opt : New file. * config/spu/spu_internals.h : New file. * config/spu/spu_intrinsics.h : New file. * config/spu/spu_mfcio.h : New file. * config/spu/t-spu-elf : New file. * config/spu/vec_types.h : New file. * config/spu/vmx2spu.h : New file. * doc/contrib.texi : Document SPU contributor. * doc/extend.texi : Document SPU extensions. * doc/invoke.texi : Document SPU options. * doc/md.texi : Document SPU constraints. libcpp/ChangeLog * configure.ac (need_64bit_hwint): Need 64bit hwint for SPU. * configure : Rebuilt. From-SVN: r119041
This commit is contained in:
Trevor Smigiel
parent
99f8a411dc
commit
85d9c13c20
37 changed files with 18240 additions and 2 deletions
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@ -1,3 +1,8 @@
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2006-11-20 Trevor Smigiel <trevor_smigiel@playstation.sony.com>
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* configure.in (skipdirs) : Don't build target-libiberty for SPU.
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* configure : Rebuilt.
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2006-11-20 Trevor Smigiel <trevor_smigiel@playstation.sony.com>
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* MAINTAINERS (Write After Approval): Add myself.
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3
configure
vendored
3
configure
vendored
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@ -1598,6 +1598,9 @@ case "${target}" in
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;;
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sparc-*-solaris* | sparc64-*-solaris* | sparcv9-*-solaris*)
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;;
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spu-*-*)
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skipdirs="target-libiberty"
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;;
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v810-*-*)
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noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
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;;
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@ -774,6 +774,9 @@ case "${target}" in
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;;
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sparc-*-solaris* | sparc64-*-solaris* | sparcv9-*-solaris*)
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;;
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spu-*-*)
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skipdirs="target-libiberty"
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;;
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v810-*-*)
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noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
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;;
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@ -1,3 +1,42 @@
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2006-11-20 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
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Russell Olsen <Russell_Olsen@playstation.sony.com>
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Dmitri Makarov <Dmitri_Makarov@playstation.sony.com>
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Yukishige Shibata <shibata@rd.scei.sony.co.jp>
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Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
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Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
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Andrew Pinski <Andrew_Pinski@playstation.sony.com>
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* config.gcc : Add target for SPU.
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* config/spu/constraints.md : New file.
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* config/spu/crt0.c : New file.
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* config/spu/crtend.c : New file.
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* config/spu/crti.asm : New file.
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* config/spu/crtn.asm : New file.
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* config/spu/float_unsdidf.c : New file.
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* config/spu/float_unssidf.c : New file.
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* config/spu/predicates.md : New file.
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* config/spu/spu-builtins.def : New file.
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* config/spu/spu-builtins.h : New file.
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* config/spu/spu-builtins.md : New file.
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* config/spu/spu-c.c : New file.
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* config/spu/spu-elf.h : New file.
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* config/spu/spu-modes.def : New file.
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* config/spu/spu-protos.h : New file.
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* config/spu/spu.c : New file.
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* config/spu/spu.h : New file.
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* config/spu/spu.md : New file.
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* config/spu/spu.opt : New file.
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* config/spu/spu_internals.h : New file.
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* config/spu/spu_intrinsics.h : New file.
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* config/spu/spu_mfcio.h : New file.
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* config/spu/t-spu-elf : New file.
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* config/spu/vec_types.h : New file.
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* config/spu/vmx2spu.h : New file.
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* doc/contrib.texi : Document SPU contributor.
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* doc/extend.texi : Document SPU extensions.
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* doc/invoke.texi : Document SPU options.
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* doc/md.texi : Document SPU constraints.
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2006-11-21 Zdenek Dvorak <dvorakz@suse.cz>
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* cfgloopmanip.c (add_loop, duplicate_loop): Do not set level
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@ -321,6 +321,10 @@ sparc64*-*-*)
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sparc*-*-*)
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cpu_type=sparc
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;;
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spu*-*-*)
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cpu_type=spu
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need_64bit_hwint=yes
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;;
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s390*-*-*)
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cpu_type=s390
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need_64bit_hwint=yes
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@ -2326,6 +2330,14 @@ sparc64-*-netbsd*)
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extra_options="${extra_options} sparc/long-double-switch.opt"
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tmake_file="${tmake_file} sparc/t-netbsd64"
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;;
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spu-*-elf*)
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tm_file="dbxelf.h elfos.h spu/spu-elf.h spu/spu.h"
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tmake_file="spu/t-spu-elf"
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extra_headers="spu_intrinsics.h spu_internals.h vmx2spu.h spu_mfcio.h vec_types.h"
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extra_modes=spu/spu-modes.def
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c_target_objs="${c_target_objs} spu-c.o"
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cxx_target_objs="${cxx_target_objs} spu-c.o"
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;;
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strongarm-*-elf*)
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tm_file="arm/strongarm-elf.h dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h"
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tmake_file="arm/t-arm arm/t-strongarm-elf"
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150
gcc/config/spu/constraints.md
Normal file
150
gcc/config/spu/constraints.md
Normal file
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@ -0,0 +1,150 @@
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;; Constraint definitions for SPU
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;; Copyright (C) 2006 Free Software Foundation, Inc.
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;;
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;; This file is free software; you can redistribute it and/or modify it under
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;; the terms of the GNU General Public License as published by the Free
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;; Software Foundation; either version 2 of the License, or (at your option)
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;; any later version.
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;; This file is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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;; for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with this file; see the file COPYING. If not, write to the Free
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;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
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;; 02110-1301, USA.
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;; GCC standard constraints: g, i, m, n, o, p, r, s, E-H, I-P, V, X
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;; unused for SPU: E-H, L, Q, d, e, h, j-l, q, t-z
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;; For most immediate constraints we have 3 variations to deal with the
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;; fact const_int has no mode. One variation treats const_int as 32 bit,
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;; another treats it as 64 bit, and the third sign extends it to 128 bit.
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(define_constraint "A"
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"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value."
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(ior (and (match_code "const_int,const_double,const_vector")
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(match_test "immediate_load_p (op, SImode)"))
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(and (match_test "!TARGET_LARGE_MEM && !flag_pic")
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(ior (match_code "symbol_ref,label_ref")
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(and (match_code "const")
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(match_test "legitimate_const (op, 0)"))))))
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(define_constraint "B"
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"An immediate for arithmetic instructions (e.g., ai, ceqi). const_int is treated as a 32 bit value."
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(and (match_code "const_int,const_double,const_vector")
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(match_test "arith_immediate_p (op, SImode, -0x200, 0x1ff)")))
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(define_constraint "C"
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"An immediate for and/xor/or instructions. const_int is treated as a 32 bit value."
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(and (match_code "const_int,const_double,const_vector")
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(match_test "logical_immediate_p (op, SImode)")))
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(define_constraint "D"
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"An immediate for iohl instruction. const_int is treated as a 32 bit value."
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(and (match_code "const_int,const_double,const_vector")
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(match_test "iohl_immediate_p (op, SImode)")))
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(define_constraint "U"
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"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit."
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(and (match_code "const_int,const_double,const_vector")
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(match_test "immediate_load_p (op, TImode)")))
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(define_constraint "W"
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"An immediate for shift and rotate instructions. const_int is treated as a 32 bit value."
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(and (match_code "const_int,const_double,const_vector")
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(match_test "arith_immediate_p (op, SImode, -0x40, 0x3f)")))
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(define_constraint "Y"
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"An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit."
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(and (match_code "const_int,const_double,const_vector")
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(match_test "logical_immediate_p (op, TImode)")))
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(define_constraint "Z"
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"An immediate for iohl instruction. const_int is sign extended to 128 bit."
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(and (match_code "const_int,const_double,const_vector")
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(match_test "iohl_immediate_p (op, TImode)")))
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(define_constraint "a"
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"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value."
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(and (match_code "const_int")
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(match_test "immediate_load_p (op, DImode)")))
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(define_constraint "c"
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"An immediate for and/xor/or instructions. const_int is treated as a 64 bit value."
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(and (match_code "const_int")
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(match_test "logical_immediate_p (op, DImode)")))
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(define_constraint "d"
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"An immediate for iohl instruction. const_int is treated as a 64 bit value."
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(and (match_code "const_int")
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(match_test "iohl_immediate_p (op, DImode)")))
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(define_constraint "f"
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"An immediate which can be loaded with fsmbi."
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(and (match_code "const_int,const_double,const_vector")
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(match_test "fsmbi_const_p (op)")))
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;; Integer constraints
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(define_constraint "I"
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"A constant in the range [-64, 63] for shift/rotate instructions."
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(and (match_code "const_int")
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(match_test "ival >= -0x40 && ival <= 0x3f")))
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(define_constraint "J"
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"An unsigned 7-bit constant for conversion/nop/channel instructions."
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(and (match_code "const_int")
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(match_test "ival >= 0 && ival <= 0x7f")))
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(define_constraint "K"
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"A signed 10-bit constant for most arithmetic instructions."
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(and (match_code "const_int")
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(match_test "ival >= -0x200 && ival <= 0x1ff")))
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(define_constraint "M"
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"A signed 16 bit immediate for @code{stop}."
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(and (match_code "const_int")
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(match_test "ival >= -0x8000ll && ival <= 0x7fffll")))
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(define_constraint "N"
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"An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}."
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(and (match_code "const_int")
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(match_test "ival >= 0 && ival <= 0xffff")))
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(define_constraint "O"
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"An unsigned 7-bit constant whose 3 least significant bits are 0."
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(and (match_code "const_int")
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(match_test "ival >= 0 && ival <= 0x7f && (ival & 7) == 0")))
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(define_constraint "P"
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"An unsigned 3-bit constant for 16-byte rotates and shifts"
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(and (match_code "const_int")
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(match_test "ival >= 0 && ival <= 7")))
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;; Memory constraints
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(define_memory_constraint "R"
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"Call operand, reg, for indirect calls"
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(and (match_code "mem")
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(match_test "GET_CODE(XEXP(op, 0)) == REG")))
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|
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(define_memory_constraint "S"
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"Call operand, symbol, for relative calls."
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(and (match_code "mem")
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(match_test "!TARGET_LARGE_MEM
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&& ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
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|| GET_CODE (XEXP (op, 0)) == LABEL_REF))")))
|
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|
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(define_memory_constraint "T"
|
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"Call operand, const_int, for absolute calls."
|
||||
(and (match_code "mem")
|
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(match_test "GET_CODE (XEXP (op, 0)) == CONST_INT
|
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&& INTVAL (XEXP (op, 0)) >= 0
|
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&& INTVAL (XEXP (op, 0)) <= 0x3ffff")))
|
||||
|
||||
|
||||
130
gcc/config/spu/crt0.c
Normal file
130
gcc/config/spu/crt0.c
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
/* As a special exception, if you link this library with files compiled with
|
||||
GCC to produce an executable, this does not cause the resulting executable
|
||||
to be covered by the GNU General Public License. The exception does not
|
||||
however invalidate any other reasons why the executable file might be covered
|
||||
by the GNU General Public License. */
|
||||
|
||||
extern int main(int, unsigned long long, unsigned long long);
|
||||
void _start(int, unsigned long long, unsigned long long) __attribute__((__naked__));
|
||||
|
||||
extern void exit(int);
|
||||
|
||||
void _exit(int) __attribute__((__naked__));
|
||||
|
||||
typedef void (*func_ptr) (void);
|
||||
typedef __attribute__ ((__vector_size__(16))) unsigned int vec_uint4;
|
||||
|
||||
extern vec_uint4 __stack[];
|
||||
register vec_uint4 si_sp __asm__("$sp");
|
||||
register unsigned int si_r2 __asm__("$2");
|
||||
|
||||
extern char _end[];
|
||||
|
||||
/* If we want these aligned we need to do it in the linker script. */
|
||||
func_ptr __CTOR_LIST__[1]
|
||||
__attribute__ ((__section__(".ctors"), __aligned__(4)))
|
||||
= { (func_ptr) (-1) };
|
||||
|
||||
static func_ptr __DTOR_LIST__[1]
|
||||
__attribute__((__section__(".dtors"), __aligned__(4)))
|
||||
= { (func_ptr) (-1) };
|
||||
|
||||
|
||||
/* According to the BE Linux ABI an SPU module is called with these
|
||||
* parameters. Also, $2 is set to the Available Stack Size. */
|
||||
void
|
||||
_start(int spu_id,
|
||||
unsigned long long param,
|
||||
unsigned long long env)
|
||||
{
|
||||
unsigned int stack_size;
|
||||
unsigned int sp = (unsigned int)(__stack - 2);
|
||||
|
||||
/* Initialize the stack. __stack has been set to point to the top
|
||||
quadword of the stack. The ABI requires at least a NULL terminated
|
||||
back chain and lr save area. For example:
|
||||
+----------------+
|
||||
| 0 |
|
||||
+----------------+ <- __stack (e.g., 0x3fff0)
|
||||
| space for $lr |
|
||||
+----------------+
|
||||
| back chain |
|
||||
+----------------+ <- $sp (e.g., __stack - 32, 0x3ffd0)
|
||||
*/
|
||||
__stack[0] = (vec_uint4){0, 0, 0, 0};
|
||||
__stack[-1] = (vec_uint4){0, 0, 0, 0};
|
||||
|
||||
/* Initialize the Available Stack Size word of the Stack Pointer
|
||||
* information register. The BE Linux ABI passes the stack size in
|
||||
* $2, or use everything up to _end if $2 == 0. */
|
||||
stack_size = si_r2 == 0 ? sp - (unsigned int)_end : si_r2;
|
||||
|
||||
__stack[-2] = (vec_uint4){(unsigned int)__stack, stack_size, 0, 0};
|
||||
|
||||
si_sp = (vec_uint4){sp, stack_size, 0, 0};
|
||||
|
||||
|
||||
{
|
||||
extern func_ptr __CTOR_END__[];
|
||||
func_ptr *p;
|
||||
|
||||
/* The compiler assumes all symbols are 16 byte aligned, which is
|
||||
* not the case for __CTOR_END__. This inline assembly makes sure
|
||||
* the address is loaded into a register for which the compiler does
|
||||
* not assume anything about alignment. */
|
||||
__asm__ ("\n" : "=r" (p) : "0" (__CTOR_END__ - 1));
|
||||
|
||||
for (; *p != (func_ptr) -1; p--)
|
||||
(*p) ();
|
||||
}
|
||||
|
||||
exit(main(spu_id, param, env));
|
||||
__asm__ volatile ( " stop 0x20ff");
|
||||
}
|
||||
|
||||
/* C99 requires _Exit */
|
||||
void _Exit(int) __attribute__((__weak__, __alias__("_exit")));
|
||||
|
||||
void
|
||||
_exit(int rc)
|
||||
{
|
||||
{
|
||||
static func_ptr *p = 0;
|
||||
if (!p)
|
||||
{
|
||||
/* See comment for __CTOR_END__ above. */
|
||||
__asm__ ("" : "=r" (p) : "0" (__DTOR_LIST__ + 1));
|
||||
for (; *p; p++)
|
||||
(*p) ();
|
||||
}
|
||||
}
|
||||
/* Some self modifying code to return 'rc' in the 'stop' insn. */
|
||||
__asm__ volatile (
|
||||
" ori $3, %0,0\n"
|
||||
" lqr $4, 1f\n"
|
||||
" cbd $5, 1f+3($sp)\n"
|
||||
" shufb $0, %0, $4, $5\n"
|
||||
" stqr $0, 1f\n"
|
||||
" sync\n"
|
||||
"1:\n"
|
||||
" stop 0x2000\n"
|
||||
: : "r" (rc) );
|
||||
}
|
||||
|
||||
32
gcc/config/spu/crtend.c
Normal file
32
gcc/config/spu/crtend.c
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
/* As a special exception, if you link this library with files compiled with
|
||||
GCC to produce an executable, this does not cause the resulting executable
|
||||
to be covered by the GNU General Public License. The exception does not
|
||||
however invalidate any other reasons why the executable file might be covered
|
||||
by the GNU General Public License. */
|
||||
|
||||
typedef void (*func_ptr) (void);
|
||||
|
||||
func_ptr __CTOR_END__[1]
|
||||
__attribute__ ((section(".ctors"), aligned(sizeof(func_ptr))))
|
||||
= { (func_ptr) (0) };
|
||||
|
||||
func_ptr __DTOR_END__[1]
|
||||
__attribute__((section(".dtors"), aligned(sizeof(func_ptr))))
|
||||
= { (func_ptr) (0) };
|
||||
53
gcc/config/spu/crti.asm
Normal file
53
gcc/config/spu/crti.asm
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
# Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
#
|
||||
# This file is free software; you can redistribute it and/or modify it under
|
||||
# the terms of the GNU General Public License as published by the Free
|
||||
# Software Foundation; either version 2 of the License, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
# for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this file; see the file COPYING. If not, write to the Free
|
||||
# Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
# 02110-1301, USA. */
|
||||
#
|
||||
# As a special exception, if you link this library with files
|
||||
# compiled with GCC to produce an executable, this does not cause
|
||||
# the resulting executable to be covered by the GNU General Public License.
|
||||
# This exception does not however invalidate any other reasons why
|
||||
# the executable file might be covered by the GNU General Public License.
|
||||
#
|
||||
|
||||
# This file just make a stack frame for the contents of the .fini and
|
||||
# .init sections. Users may put any desired instructions in those
|
||||
# sections.
|
||||
|
||||
# Note - this macro is complimented by the FUNC_END macro
|
||||
# in crtn.asm. If you change this macro you must also change
|
||||
# that macro match.
|
||||
.macro FUNC_START
|
||||
# Create a stack frame and save any call-preserved registers
|
||||
ai $sp, $sp, -16
|
||||
stqd $lr, 0($sp)
|
||||
.endm
|
||||
|
||||
.file "crti.asm"
|
||||
|
||||
.section ".init"
|
||||
.align 2
|
||||
.global _init
|
||||
_init:
|
||||
FUNC_START
|
||||
|
||||
|
||||
.section ".fini"
|
||||
.align 2
|
||||
.global _fini
|
||||
_fini:
|
||||
FUNC_START
|
||||
|
||||
# end of crti.asm
|
||||
54
gcc/config/spu/crtn.asm
Normal file
54
gcc/config/spu/crtn.asm
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
# Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
#
|
||||
# This file is free software; you can redistribute it and/or modify it under
|
||||
# the terms of the GNU General Public License as published by the Free
|
||||
# Software Foundation; either version 2 of the License, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
# for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this file; see the file COPYING. If not, write to the Free
|
||||
# Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
# 02110-1301, USA. */
|
||||
#
|
||||
# As a special exception, if you link this library with files
|
||||
# compiled with GCC to produce an executable, this does not cause
|
||||
# the resulting executable to be covered by the GNU General Public License.
|
||||
# This exception does not however invalidate any other reasons why
|
||||
# the executable file might be covered by the GNU General Public License.
|
||||
#
|
||||
|
||||
# This file just makes sure that the .fini and .init sections do in
|
||||
# fact return. Users may put any desired instructions in those sections.
|
||||
# This file is the last thing linked into any executable.
|
||||
|
||||
# Note - this macro is complimented by the FUNC_START macro
|
||||
# in crti.asm. If you change this macro you must also change
|
||||
# that macro match.
|
||||
#
|
||||
# Note - we do not try any fancy optimisations of the return
|
||||
# sequences here, it is just not worth it. Instead keep things
|
||||
# simple. Restore all the save resgisters, including the link
|
||||
# register and then perform the correct function return instruction.
|
||||
.macro FUNC_END
|
||||
lqd $lr, 0($sp)
|
||||
ai $sp, $sp, 16
|
||||
bi $lr
|
||||
.endm
|
||||
|
||||
|
||||
.file "crtn.asm"
|
||||
|
||||
.section ".init"
|
||||
;;
|
||||
FUNC_END
|
||||
|
||||
.section ".fini"
|
||||
;;
|
||||
FUNC_END
|
||||
|
||||
# end of crtn.asm
|
||||
56
gcc/config/spu/float_unsdidf.c
Normal file
56
gcc/config/spu/float_unsdidf.c
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
/* As a special exception, if you link this library with files compiled with
|
||||
GCC to produce an executable, this does not cause the resulting executable
|
||||
to be covered by the GNU General Public License. The exception does not
|
||||
however invalidate any other reasons why the executable file might be covered
|
||||
by the GNU General Public License. */
|
||||
|
||||
#include <spu_intrinsics.h>
|
||||
const unsigned char __didf_scale[16] __attribute__ ((__aligned__ (16))) = {
|
||||
0x00, 0x00, 0x04, 0x3e,
|
||||
0x00, 0x00, 0x04, 0x1e,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
const unsigned char __didf_pat[16] __attribute__ ((__aligned__ (16))) = {
|
||||
0x02, 0x03, 0x10, 0x11,
|
||||
0x12, 0x13, 0x80, 0x80,
|
||||
0x06, 0x07, 0x14, 0x15,
|
||||
0x16, 0x17, 0x80, 0x80
|
||||
};
|
||||
|
||||
/* double __float_unsdidf (unsigned long long int)
|
||||
Construct two exact doubles representing the high and low parts (in
|
||||
parallel), then add them. */
|
||||
qword __float_unsdidf (qword DI);
|
||||
qword
|
||||
__float_unsdidf (qword DI)
|
||||
{
|
||||
qword t0, t1, t2, t3, t4, t5, t6, t7, t8;
|
||||
t0 = si_clz (DI);
|
||||
t1 = si_shl (DI, t0);
|
||||
t2 = si_ceqi (t0, 32);
|
||||
t3 = si_sf (t0, *(qword *) __didf_scale);
|
||||
t4 = si_a (t1, t1);
|
||||
t5 = si_andc (t3, t2);
|
||||
t6 = si_shufb (t5, t4, *(qword *) __didf_pat);
|
||||
t7 = si_shlqbii (t6, 4);
|
||||
t8 = si_shlqbyi (t7, 8);
|
||||
return si_dfa (t7, t8);
|
||||
}
|
||||
47
gcc/config/spu/float_unssidf.c
Normal file
47
gcc/config/spu/float_unssidf.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
/* As a special exception, if you link this library with files compiled with
|
||||
GCC to produce an executable, this does not cause the resulting executable
|
||||
to be covered by the GNU General Public License. The exception does not
|
||||
however invalidate any other reasons why the executable file might be covered
|
||||
by the GNU General Public License. */
|
||||
|
||||
#include <spu_intrinsics.h>
|
||||
const unsigned char __sidf_pat[16] __attribute__ ((__aligned__ (16))) = {
|
||||
0x02, 0x03, 0x10, 0x11,
|
||||
0x12, 0x13, 0x80, 0x80,
|
||||
0x06, 0x07, 0x14, 0x15,
|
||||
0x16, 0x17, 0x80, 0x80
|
||||
};
|
||||
|
||||
/* double __float_unssidf (unsigned int SI) */
|
||||
qword __float_unssidf (qword SI);
|
||||
qword
|
||||
__float_unssidf (qword SI)
|
||||
{
|
||||
qword t0, t1, t2, t3, t4, t5, t6, t7;
|
||||
t0 = si_clz (SI);
|
||||
t1 = si_il (1054);
|
||||
t2 = si_shl (SI, t0);
|
||||
t3 = si_ceqi (t0, 32);
|
||||
t4 = si_sf (t0, t1);
|
||||
t5 = si_a (t2, t2);
|
||||
t6 = si_andc (t4, t3);
|
||||
t7 = si_shufb (t6, t5, *(qword *)__sidf_pat);
|
||||
return si_shlqbii (t7, 4);
|
||||
}
|
||||
100
gcc/config/spu/predicates.md
Normal file
100
gcc/config/spu/predicates.md
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
;; Predicate definitions for CELL SPU
|
||||
;; Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
;;
|
||||
;; This file is free software; you can redistribute it and/or modify it under
|
||||
;; the terms of the GNU General Public License as published by the Free
|
||||
;; Software Foundation; either version 2 of the License, or (at your option)
|
||||
;; any later version.
|
||||
|
||||
;; This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
;; for more details.
|
||||
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with this file; see the file COPYING. If not, write to the Free
|
||||
;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
;; 02110-1301, USA.
|
||||
|
||||
(define_predicate "spu_reg_operand"
|
||||
(and (match_operand 0 "register_operand")
|
||||
(ior (not (match_code "subreg"))
|
||||
(match_test "valid_subreg (op)"))))
|
||||
|
||||
(define_predicate "spu_nonimm_operand"
|
||||
(and (match_operand 0 "nonimmediate_operand")
|
||||
(ior (not (match_code "subreg"))
|
||||
(match_test "valid_subreg (op)"))))
|
||||
|
||||
(define_predicate "spu_nonmem_operand"
|
||||
(and (match_operand 0 "nonmemory_operand")
|
||||
(ior (not (match_code "subreg"))
|
||||
(match_test "valid_subreg (op)"))))
|
||||
|
||||
(define_predicate "spu_mem_operand"
|
||||
(and (match_operand 0 "memory_operand")
|
||||
(match_test "reload_in_progress || reload_completed || aligned_mem_p (op)")))
|
||||
|
||||
(define_predicate "call_operand"
|
||||
(and (match_code "mem")
|
||||
(match_test "(!TARGET_LARGE_MEM && satisfies_constraint_S (op))
|
||||
|| (satisfies_constraint_R (op)
|
||||
&& REGNO (XEXP (op, 0)) != FRAME_POINTER_REGNUM
|
||||
&& REGNO (XEXP (op, 0)) != ARG_POINTER_REGNUM
|
||||
&& (REGNO (XEXP (op, 0)) < FIRST_PSEUDO_REGISTER
|
||||
|| REGNO (XEXP (op, 0)) > LAST_VIRTUAL_REGISTER))")))
|
||||
|
||||
(define_predicate "vec_imm_operand"
|
||||
(and (match_code "const_int,const_double,const_vector")
|
||||
(match_test "spu_legitimate_constant_p (op)")))
|
||||
|
||||
(define_predicate "spu_arith_operand"
|
||||
(match_code "reg,subreg,const_int,const_vector")
|
||||
{
|
||||
if (spu_reg_operand (op, mode))
|
||||
return 1;
|
||||
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_VECTOR)
|
||||
return arith_immediate_p (op, mode, -0x200, 0x1ff);
|
||||
return 0;
|
||||
})
|
||||
|
||||
(define_predicate "spu_logical_operand"
|
||||
(match_code "reg,subreg,const_int,const_double,const_vector")
|
||||
{
|
||||
if (spu_reg_operand (op, mode))
|
||||
return 1;
|
||||
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
|
||||
|| GET_CODE (op) == CONST_VECTOR)
|
||||
return logical_immediate_p (op, mode);
|
||||
return 0;
|
||||
})
|
||||
|
||||
(define_predicate "spu_ior_operand"
|
||||
(match_code "reg,subreg,const_int,const_double,const_vector")
|
||||
{
|
||||
if (spu_reg_operand (op, mode))
|
||||
return 1;
|
||||
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
|
||||
|| GET_CODE (op) == CONST_VECTOR)
|
||||
return logical_immediate_p (op, mode)
|
||||
|| iohl_immediate_p (op, mode);
|
||||
return 0;
|
||||
})
|
||||
|
||||
(define_predicate "spu_shift_operand"
|
||||
(match_code "reg,subreg,const_int,const_vector")
|
||||
{
|
||||
if (spu_reg_operand (op, mode))
|
||||
return 1;
|
||||
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_VECTOR)
|
||||
return arith_immediate_p (op, mode, -0x40, 0x3f);
|
||||
return 0;
|
||||
})
|
||||
|
||||
;; Return 1 if OP is a comparison operation that is valid for a branch insn.
|
||||
;; We only check the opcode against the mode of the register value here.
|
||||
(define_predicate "branch_comparison_operator"
|
||||
(and (match_code "eq,ne")
|
||||
(ior (match_test "GET_MODE (XEXP (op, 0)) == HImode")
|
||||
(match_test "GET_MODE (XEXP (op, 0)) == SImode"))))
|
||||
|
||||
715
gcc/config/spu/spu-builtins.def
Normal file
715
gcc/config/spu/spu-builtins.def
Normal file
|
|
@ -0,0 +1,715 @@
|
|||
/* Definitions of builtin fuctions for the Synergistic Processing Unit (SPU). */
|
||||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
|
||||
/* The first argument to these macros is the return type of the builtin,
|
||||
* the rest are arguments of the builtin. */
|
||||
#define _A1(a) {a, SPU_BTI_END_OF_PARAMS}
|
||||
#define _A2(a,b) {a, b, SPU_BTI_END_OF_PARAMS}
|
||||
#define _A3(a,b,c) {a, b, c, SPU_BTI_END_OF_PARAMS}
|
||||
#define _A4(a,b,c,d) {a, b, c, d, SPU_BTI_END_OF_PARAMS}
|
||||
|
||||
/* definitions to support si intrinisic functions: (These and other builtin
|
||||
* definitions must preceed definitions of the overloaded generic intrinsics */
|
||||
|
||||
DEF_BUILTIN (SI_LQD, CODE_FOR_spu_lqd, "si_lqd", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10_4))
|
||||
DEF_BUILTIN (SI_LQX, CODE_FOR_spu_lqx, "si_lqx", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_LQA, CODE_FOR_spu_lqa, "si_lqa", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_U16_2))
|
||||
DEF_BUILTIN (SI_LQR, CODE_FOR_spu_lqr, "si_lqr", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_S16_2))
|
||||
DEF_BUILTIN (SI_STQD, CODE_FOR_spu_stqd, "si_stqd", B_INSN, _A4(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10_4))
|
||||
DEF_BUILTIN (SI_STQX, CODE_FOR_spu_stqx, "si_stqx", B_INSN, _A4(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_STQA, CODE_FOR_spu_stqa, "si_stqa", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_U16_2))
|
||||
DEF_BUILTIN (SI_STQR, CODE_FOR_spu_stqr, "si_stqr", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_S16_2))
|
||||
DEF_BUILTIN (SI_CBD, CODE_FOR_spu_cbx, "si_cbd", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S7))
|
||||
DEF_BUILTIN (SI_CBX, CODE_FOR_spu_cbx, "si_cbx", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CHD, CODE_FOR_spu_chx, "si_chd", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S7))
|
||||
DEF_BUILTIN (SI_CHX, CODE_FOR_spu_chx, "si_chx", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CWD, CODE_FOR_spu_cwx, "si_cwd", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S7))
|
||||
DEF_BUILTIN (SI_CWX, CODE_FOR_spu_cwx, "si_cwx", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CDD, CODE_FOR_spu_cdx, "si_cdd", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S7))
|
||||
DEF_BUILTIN (SI_CDX, CODE_FOR_spu_cdx, "si_cdx", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ILH, CODE_FOR_movv8hi, "si_ilh", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_16))
|
||||
DEF_BUILTIN (SI_ILHU, CODE_FOR_spu_ilhu, "si_ilhu", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_16))
|
||||
DEF_BUILTIN (SI_IL, CODE_FOR_movv4si, "si_il", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_S16))
|
||||
DEF_BUILTIN (SI_ILA, CODE_FOR_movv4si, "si_ila", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_U18))
|
||||
DEF_BUILTIN (SI_IOHL, CODE_FOR_iorv4si3, "si_iohl", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U16))
|
||||
DEF_BUILTIN (SI_FSMBI, CODE_FOR_spu_fsmb, "si_fsmbi", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_16))
|
||||
DEF_BUILTIN (SI_AH, CODE_FOR_addv8hi3, "si_ah", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_AHI, CODE_FOR_addv8hi3, "si_ahi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_A, CODE_FOR_addv4si3, "si_a", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_AI, CODE_FOR_addv4si3, "si_ai", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_ADDX, CODE_FOR_addx_v4si, "si_addx", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CG, CODE_FOR_cg_v4si, "si_cg", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CGX, CODE_FOR_cgx_v4si, "si_cgx", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_SFH, CODE_FOR_spu_sfh, "si_sfh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_SFHI, CODE_FOR_spu_sfh, "si_sfhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_SF, CODE_FOR_spu_sf, "si_sf", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_SFI, CODE_FOR_spu_sf, "si_sfi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_SFX, CODE_FOR_spu_sfx, "si_sfx", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_BG, CODE_FOR_spu_bg, "si_bg", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_BGX, CODE_FOR_spu_bgx, "si_bgx", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_MPY, CODE_FOR_spu_mpy, "si_mpy", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_MPYU, CODE_FOR_spu_mpyu, "si_mpyu", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_MPYI, CODE_FOR_spu_mpy, "si_mpyi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_MPYUI, CODE_FOR_spu_mpyu, "si_mpyui", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_MPYA, CODE_FOR_spu_mpya, "si_mpya", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_MPYH, CODE_FOR_spu_mpyh, "si_mpyh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_MPYS, CODE_FOR_spu_mpys, "si_mpys", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_MPYHH, CODE_FOR_spu_mpyhh, "si_mpyhh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_MPYHHU, CODE_FOR_spu_mpyhhu, "si_mpyhhu", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_MPYHHA, CODE_FOR_spu_mpyhha, "si_mpyhha", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_MPYHHAU, CODE_FOR_spu_mpyhhau, "si_mpyhhau", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CLZ, CODE_FOR_clzv4si2, "si_clz", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CNTB, CODE_FOR_cntb_v16qi, "si_cntb", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FSMB, CODE_FOR_spu_fsmb, "si_fsmb", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FSMH, CODE_FOR_spu_fsmh, "si_fsmh", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FSM, CODE_FOR_spu_fsm, "si_fsm", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_GBB, CODE_FOR_spu_gbb, "si_gbb", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_GBH, CODE_FOR_spu_gbh, "si_gbh", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_GB, CODE_FOR_spu_gb, "si_gb", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_AVGB, CODE_FOR_spu_avgb, "si_avgb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ABSDB, CODE_FOR_spu_absdb, "si_absdb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_SUMB, CODE_FOR_spu_sumb, "si_sumb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_XSBH, CODE_FOR_spu_xsbh, "si_xsbh", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_XSHW, CODE_FOR_spu_xshw, "si_xshw", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_XSWD, CODE_FOR_spu_xswd, "si_xswd", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_AND, CODE_FOR_andv16qi3, "si_and", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ANDC, CODE_FOR_andc_v16qi, "si_andc", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ANDBI, CODE_FOR_andv16qi3, "si_andbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_ANDHI, CODE_FOR_andv8hi3, "si_andhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_ANDI, CODE_FOR_andv4si3, "si_andi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_OR, CODE_FOR_iorv16qi3, "si_or", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ORC, CODE_FOR_orc_v16qi, "si_orc", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ORBI, CODE_FOR_iorv16qi3, "si_orbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_ORHI, CODE_FOR_iorv8hi3, "si_orhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_ORI, CODE_FOR_iorv4si3, "si_ori", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_ORX, CODE_FOR_spu_orx, "si_orx", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_XOR, CODE_FOR_xorv16qi3, "si_xor", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_XORBI, CODE_FOR_xorv16qi3, "si_xorbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_XORHI, CODE_FOR_xorv8hi3, "si_xorhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_XORI, CODE_FOR_xorv4si3, "si_xori", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_NAND, CODE_FOR_nand_v16qi, "si_nand", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_NOR, CODE_FOR_nor_v16qi, "si_nor", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_EQV, CODE_FOR_eqv_v16qi, "si_eqv", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_SELB, CODE_FOR_selb, "si_selb", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_SHUFB, CODE_FOR_shufb, "si_shufb", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_SHLH, CODE_FOR_ashlv8hi3, "si_shlh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_SHLHI, CODE_FOR_ashlv8hi3, "si_shlhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_SHL, CODE_FOR_ashlv4si3, "si_shl", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_SHLI, CODE_FOR_ashlv4si3, "si_shli", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_SHLQBI, CODE_FOR_shlqbi_ti, "si_shlqbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_SHLQBII, CODE_FOR_shlqbi_ti, "si_shlqbii", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_SHLQBY, CODE_FOR_shlqby_ti, "si_shlqby", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_SHLQBYI, CODE_FOR_shlqby_ti, "si_shlqbyi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_SHLQBYBI, CODE_FOR_shlqbybi_ti, "si_shlqbybi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTH, CODE_FOR_rotlv8hi3, "si_roth", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTHI, CODE_FOR_rotlv8hi3, "si_rothi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_ROT, CODE_FOR_rotlv4si3, "si_rot", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTI, CODE_FOR_rotlv4si3, "si_roti", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_ROTQBY, CODE_FOR_rotqby_ti, "si_rotqby", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTQBYI, CODE_FOR_rotqby_ti, "si_rotqbyi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_ROTQBYBI, CODE_FOR_rotqbybi_ti, "si_rotqbybi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTQBI, CODE_FOR_rotqbi_ti, "si_rotqbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTQBII, CODE_FOR_rotqbi_ti, "si_rotqbii", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_ROTHM, CODE_FOR_rotm_v8hi, "si_rothm", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTHMI, CODE_FOR_rotm_v8hi, "si_rothmi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_ROTM, CODE_FOR_rotm_v4si, "si_rotm", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTMI, CODE_FOR_rotm_v4si, "si_rotmi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_ROTQMBY, CODE_FOR_rotqmby_ti, "si_rotqmby", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTQMBYI, CODE_FOR_rotqmby_ti, "si_rotqmbyi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_ROTQMBI, CODE_FOR_rotqmbi_ti, "si_rotqmbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTQMBII, CODE_FOR_rotqmbi_ti, "si_rotqmbii", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_ROTQMBYBI, CODE_FOR_rotqmbybi_ti, "si_rotqmbybi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTMAH, CODE_FOR_rotma_v8hi, "si_rotmah", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTMAHI, CODE_FOR_rotma_v8hi, "si_rotmahi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_ROTMA, CODE_FOR_rotma_v4si, "si_rotma", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_ROTMAI, CODE_FOR_rotma_v4si, "si_rotmai", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
|
||||
DEF_BUILTIN (SI_HEQ, CODE_FOR_spu_heq, "si_heq", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_HEQI, CODE_FOR_spu_heq, "si_heqi", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_HGT, CODE_FOR_spu_hgt, "si_hgt", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_HGTI, CODE_FOR_spu_hgt, "si_hgti", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_HLGT, CODE_FOR_spu_hlgt, "si_hlgt", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_HLGTI, CODE_FOR_spu_hlgt, "si_hlgti", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_CEQB, CODE_FOR_ceq_v16qi, "si_ceqb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CEQBI, CODE_FOR_ceq_v16qi, "si_ceqbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_CEQH, CODE_FOR_ceq_v8hi, "si_ceqh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CEQHI, CODE_FOR_ceq_v8hi, "si_ceqhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_CEQ, CODE_FOR_ceq_v4si, "si_ceq", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CEQI, CODE_FOR_ceq_v4si, "si_ceqi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_CGTB, CODE_FOR_cgt_v16qi, "si_cgtb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CGTBI, CODE_FOR_cgt_v16qi, "si_cgtbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_CGTH, CODE_FOR_cgt_v8hi, "si_cgth", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CGTHI, CODE_FOR_cgt_v8hi, "si_cgthi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_CGT, CODE_FOR_cgt_v4si, "si_cgt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CGTI, CODE_FOR_cgt_v4si, "si_cgti", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_CLGTB, CODE_FOR_clgt_v16qi, "si_clgtb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CLGTBI, CODE_FOR_clgt_v16qi, "si_clgtbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_CLGTH, CODE_FOR_clgt_v8hi, "si_clgth", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CLGTHI, CODE_FOR_clgt_v8hi, "si_clgthi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_CLGT, CODE_FOR_clgt_v4si, "si_clgt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CLGTI, CODE_FOR_clgt_v4si, "si_clgti", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
|
||||
DEF_BUILTIN (SI_FA, CODE_FOR_addv4sf3, "si_fa", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_DFA, CODE_FOR_addv2df3, "si_dfa", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FS, CODE_FOR_subv4sf3, "si_fs", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_DFS, CODE_FOR_subv2df3, "si_dfs", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FM, CODE_FOR_mulv4sf3, "si_fm", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_DFM, CODE_FOR_mulv2df3, "si_dfm", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FMA, CODE_FOR_fma_v4sf, "si_fma", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_DFMA, CODE_FOR_fma_v2df, "si_dfma", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_DFNMA, CODE_FOR_fnma_v2df, "si_dfnma", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FNMS, CODE_FOR_fnms_v4sf, "si_fnms", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_DFNMS, CODE_FOR_fnms_v2df, "si_dfnms", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FMS, CODE_FOR_fms_v4sf, "si_fms", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_DFMS, CODE_FOR_fms_v2df, "si_dfms", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FREST, CODE_FOR_frest_v4sf, "si_frest", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FRSQEST, CODE_FOR_frsqest_v4sf, "si_frsqest", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FI, CODE_FOR_fi_v4sf, "si_fi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_CSFLT, CODE_FOR_spu_csflt, "si_csflt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U7))
|
||||
DEF_BUILTIN (SI_CFLTS, CODE_FOR_spu_cflts, "si_cflts", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U7))
|
||||
DEF_BUILTIN (SI_CUFLT, CODE_FOR_spu_cuflt, "si_cuflt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U7))
|
||||
DEF_BUILTIN (SI_CFLTU, CODE_FOR_spu_cfltu, "si_cfltu", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U7))
|
||||
DEF_BUILTIN (SI_FRDS, CODE_FOR_spu_frds, "si_frds", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FESD, CODE_FOR_spu_fesd, "si_fesd", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FCEQ, CODE_FOR_ceq_v4sf, "si_fceq", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FCMEQ, CODE_FOR_cmeq_v4sf, "si_fcmeq", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FCGT, CODE_FOR_cgt_v4sf, "si_fcgt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FCMGT, CODE_FOR_cmgt_v4sf, "si_fcmgt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_STOP, CODE_FOR_spu_stop, "si_stop", B_INSN, _A2(SPU_BTI_VOID, SPU_BTI_U14))
|
||||
DEF_BUILTIN (SI_STOPD, CODE_FOR_spu_stopd, "si_stopd", B_INSN, _A4(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_LNOP, CODE_FOR_lnop, "si_lnop", B_INSN, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SI_NOP, CODE_FOR_nop, "si_nop", B_INSN, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SI_SYNC, CODE_FOR_sync, "si_sync", B_INSN, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SI_SYNCC, CODE_FOR_syncc, "si_syncc", B_INSN, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SI_DSYNC, CODE_FOR_dsync, "si_dsync", B_INSN, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SI_MFSPR, CODE_FOR_spu_mfspr, "si_mfspr", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_U7))
|
||||
DEF_BUILTIN (SI_MTSPR, CODE_FOR_spu_mtspr, "si_mtspr", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_U7, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FSCRRD, CODE_FOR_spu_fscrrd, "si_fscrrd", B_INSN, _A1(SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FSCRWR, CODE_FOR_spu_fscrwr, "si_fscrwr", B_INSN, _A2(SPU_BTI_VOID, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_RDCH, CODE_FOR_spu_rdch, "si_rdch", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_U7))
|
||||
DEF_BUILTIN (SI_RCHCNT, CODE_FOR_spu_rchcnt, "si_rchcnt", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_U7))
|
||||
DEF_BUILTIN (SI_WRCH, CODE_FOR_spu_wrch, "si_wrch", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_U7, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_TO_CHAR, CODE_FOR_spu_convert, "si_to_char", B_INSN, _A2(SPU_BTI_INTQI, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_TO_UCHAR, CODE_FOR_spu_convert, "si_to_uchar", B_INSN, _A2(SPU_BTI_UINTQI, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_TO_SHORT, CODE_FOR_spu_convert, "si_to_short", B_INSN, _A2(SPU_BTI_INTHI, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_TO_USHORT, CODE_FOR_spu_convert, "si_to_ushort", B_INSN, _A2(SPU_BTI_UINTHI, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_TO_INT, CODE_FOR_spu_convert, "si_to_int", B_INSN, _A2(SPU_BTI_INTSI, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_TO_UINT, CODE_FOR_spu_convert, "si_to_uint", B_INSN, _A2(SPU_BTI_UINTSI, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_TO_LONG, CODE_FOR_spu_convert, "si_to_long", B_INSN, _A2(SPU_BTI_INTDI, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_TO_ULONG, CODE_FOR_spu_convert, "si_to_ulong", B_INSN, _A2(SPU_BTI_UINTDI, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_TO_FLOAT, CODE_FOR_spu_convert, "si_to_float", B_INSN, _A2(SPU_BTI_FLOAT, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_TO_DOUBLE, CODE_FOR_spu_convert, "si_to_double", B_INSN, _A2(SPU_BTI_DOUBLE, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_TO_PTR, CODE_FOR_spu_convert, "si_to_ptr", B_INSN, _A2(SPU_BTI_PTR, SPU_BTI_QUADWORD))
|
||||
DEF_BUILTIN (SI_FROM_CHAR, CODE_FOR_spu_convert, "si_from_char", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_INTQI))
|
||||
DEF_BUILTIN (SI_FROM_UCHAR, CODE_FOR_spu_convert, "si_from_uchar", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_UINTQI))
|
||||
DEF_BUILTIN (SI_FROM_SHORT, CODE_FOR_spu_convert, "si_from_short", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_INTHI))
|
||||
DEF_BUILTIN (SI_FROM_USHORT, CODE_FOR_spu_convert, "si_from_ushort", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_UINTHI))
|
||||
DEF_BUILTIN (SI_FROM_INT, CODE_FOR_spu_convert, "si_from_int", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SI_FROM_UINT, CODE_FOR_spu_convert, "si_from_uint", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SI_FROM_LONG, CODE_FOR_spu_convert, "si_from_long", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_INTDI))
|
||||
DEF_BUILTIN (SI_FROM_ULONG, CODE_FOR_spu_convert, "si_from_ulong", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_UINTDI))
|
||||
DEF_BUILTIN (SI_FROM_FLOAT, CODE_FOR_spu_convert, "si_from_float", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_FLOAT))
|
||||
DEF_BUILTIN (SI_FROM_DOUBLE, CODE_FOR_spu_convert, "si_from_double", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_DOUBLE))
|
||||
DEF_BUILTIN (SI_FROM_PTR, CODE_FOR_spu_convert, "si_from_ptr", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_PTR))
|
||||
|
||||
/* definitions to support generic builtin functions: */
|
||||
|
||||
DEF_BUILTIN (SPU_CONVTS, CODE_FOR_spu_cflts, "spu_convts", B_INSN, _A3(SPU_BTI_V4SI, SPU_BTI_V4SF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_CONVTU, CODE_FOR_spu_cfltu, "spu_convtu", B_INSN, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_ROUNDTF, CODE_FOR_spu_frds, "spu_roundtf", B_INSN, _A2(SPU_BTI_V4SF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_MULH, CODE_FOR_spu_mpyh, "spu_mulh", B_INSN, _A3(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_MULSR, CODE_FOR_spu_mpys, "spu_mulsr", B_INSN, _A3(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_FREST, CODE_FOR_frest_v4sf, "spu_frest", B_INSN, _A2(SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_FRSQEST, CODE_FOR_frsqest_v4sf, "spu_frsqest", B_INSN, _A2(SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_NMADD, CODE_FOR_fnma_v2df, "spu_nmadd", B_INSN, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_ABSD, CODE_FOR_spu_absdb, "spu_absd", B_INSN, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_AVG, CODE_FOR_spu_avgb, "spu_avg", B_INSN, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SUMB, CODE_FOR_spu_sumb, "spu_sumb", B_INSN, _A3(SPU_BTI_UV8HI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_BISLED, CODE_FOR_spu_bisled, "spu_bisled", B_BISLED, _A3(SPU_BTI_VOID, SPU_BTI_PTR, SPU_BTI_PTR))
|
||||
DEF_BUILTIN (SPU_BISLED_D, CODE_FOR_spu_bisledd, "spu_bisled_d", B_BISLED, _A3(SPU_BTI_VOID, SPU_BTI_PTR, SPU_BTI_PTR))
|
||||
DEF_BUILTIN (SPU_BISLED_E, CODE_FOR_spu_bislede, "spu_bisled_e", B_BISLED, _A3(SPU_BTI_VOID, SPU_BTI_PTR, SPU_BTI_PTR))
|
||||
DEF_BUILTIN (SPU_CMPABSEQ, CODE_FOR_cmeq_v4sf, "spu_cmpabseq", B_INSN, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_CMPABSGT, CODE_FOR_cmgt_v4sf, "spu_cmpabsgt", B_INSN, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_IDISABLE, CODE_FOR_spu_idisable, "spu_idisable", B_INSN, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_IENABLE, CODE_FOR_spu_ienable, "spu_ienable", B_INSN, _A1(SPU_BTI_VOID))
|
||||
|
||||
/* definitions to support overloaded generic builtin functions: */
|
||||
|
||||
DEF_BUILTIN (SPU_CONVTF, CODE_FOR_nothing, "spu_convtf", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_CONVTF_0, CODE_FOR_spu_cuflt, "spu_convtf_0", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_CONVTF_1, CODE_FOR_spu_csflt, "spu_convtf_1", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_EXTEND, CODE_FOR_nothing, "spu_extend", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_EXTEND_0, CODE_FOR_spu_xsbh, "spu_extend_0", B_INTERNAL, _A2(SPU_BTI_V8HI, SPU_BTI_V16QI))
|
||||
DEF_BUILTIN (SPU_EXTEND_1, CODE_FOR_spu_xshw, "spu_extend_1", B_INTERNAL, _A2(SPU_BTI_V4SI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_EXTEND_2, CODE_FOR_spu_xswd, "spu_extend_2", B_INTERNAL, _A2(SPU_BTI_V2DI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_EXTEND_3, CODE_FOR_spu_fesd, "spu_extend_3", B_INTERNAL, _A2(SPU_BTI_V2DF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_ADD, CODE_FOR_nothing, "spu_add", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_ADD_0, CODE_FOR_addv4si3, "spu_add_0", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_ADD_1, CODE_FOR_addv4si3, "spu_add_1", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_ADD_2, CODE_FOR_addv8hi3, "spu_add_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_ADD_3, CODE_FOR_addv8hi3, "spu_add_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_ADD_4, CODE_FOR_addv4sf3, "spu_add_4", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_ADD_5, CODE_FOR_addv2df3, "spu_add_5", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_ADD_6, CODE_FOR_addv8hi3, "spu_add_6", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
|
||||
DEF_BUILTIN (SPU_ADD_7, CODE_FOR_addv8hi3, "spu_add_7", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
|
||||
DEF_BUILTIN (SPU_ADD_8, CODE_FOR_addv4si3, "spu_add_8", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_ADD_9, CODE_FOR_addv4si3, "spu_add_9", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_ADDX, CODE_FOR_nothing, "spu_addx", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_ADDX_0, CODE_FOR_addx_v4si, "spu_addx_0", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_ADDX_1, CODE_FOR_addx_v4si, "spu_addx_1", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_GENC, CODE_FOR_nothing, "spu_genc", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_GENC_0, CODE_FOR_cg_v4si, "spu_genc_0", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_GENC_1, CODE_FOR_cg_v4si, "spu_genc_1", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_GENCX, CODE_FOR_nothing, "spu_gencx", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_GENCX_0, CODE_FOR_cgx_v4si, "spu_gencx_0", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_GENCX_1, CODE_FOR_cgx_v4si, "spu_gencx_1", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_MADD, CODE_FOR_nothing, "spu_madd", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_MADD_0, CODE_FOR_spu_mpya, "spu_madd_0", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_MADD_1, CODE_FOR_fma_v4sf, "spu_madd_1", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_MADD_2, CODE_FOR_fma_v2df, "spu_madd_2", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_MSUB, CODE_FOR_nothing, "spu_msub", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_MSUB_0, CODE_FOR_fms_v4sf, "spu_msub_0", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_MSUB_1, CODE_FOR_fms_v2df, "spu_msub_1", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_MHHADD, CODE_FOR_nothing, "spu_mhhadd", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_MHHADD_0, CODE_FOR_spu_mpyhhau, "spu_mhhadd_0", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_MHHADD_1, CODE_FOR_spu_mpyhha, "spu_mhhadd_1", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_MULE, CODE_FOR_nothing, "spu_mule", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_MULE_0, CODE_FOR_spu_mpyhhu, "spu_mule_0", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_MULE_1, CODE_FOR_spu_mpyhh, "spu_mule_1", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_MUL, CODE_FOR_nothing, "spu_mul", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_MUL_0, CODE_FOR_mulv4sf3, "spu_mul_0", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_MUL_1, CODE_FOR_mulv2df3, "spu_mul_1", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_MULO, CODE_FOR_nothing, "spu_mulo", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_MULO_0, CODE_FOR_spu_mpy, "spu_mulo_0", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_MULO_1, CODE_FOR_spu_mpyu, "spu_mulo_1", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_MULO_2, CODE_FOR_spu_mpy, "spu_mulo_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_INTHI))
|
||||
DEF_BUILTIN (SPU_MULO_3, CODE_FOR_spu_mpyu, "spu_mulo_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
|
||||
DEF_BUILTIN (SPU_NMSUB, CODE_FOR_nothing, "spu_nmsub", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_NMSUB_0, CODE_FOR_fnms_v4sf, "spu_nmsub_0", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_NMSUB_1, CODE_FOR_fnms_v2df, "spu_nmsub_1", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_SUB, CODE_FOR_nothing, "spu_sub", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_SUB_0, CODE_FOR_subv8hi3, "spu_sub_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_SUB_1, CODE_FOR_subv8hi3, "spu_sub_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_SUB_2, CODE_FOR_subv4si3, "spu_sub_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_SUB_3, CODE_FOR_subv4si3, "spu_sub_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_SUB_4, CODE_FOR_subv4sf3, "spu_sub_4", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_SUB_5, CODE_FOR_subv2df3, "spu_sub_5", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_SUB_6, CODE_FOR_subv8hi3, "spu_sub_6", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UINTHI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_SUB_7, CODE_FOR_subv8hi3, "spu_sub_7", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_INTHI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_SUB_8, CODE_FOR_subv4si3, "spu_sub_8", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UINTSI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_SUB_9, CODE_FOR_subv4si3, "spu_sub_9", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_INTSI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_SUBX, CODE_FOR_nothing, "spu_subx", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_SUBX_0, CODE_FOR_sfx_v4si, "spu_subx_0", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_SUBX_1, CODE_FOR_sfx_v4si, "spu_subx_1", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_GENB, CODE_FOR_nothing, "spu_genb", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_GENB_0, CODE_FOR_bg_v4si, "spu_genb_0", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_GENB_1, CODE_FOR_bg_v4si, "spu_genb_1", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_GENBX, CODE_FOR_nothing, "spu_genbx", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_GENBX_0, CODE_FOR_bgx_v4si, "spu_genbx_0", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_GENBX_1, CODE_FOR_bgx_v4si, "spu_genbx_1", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_CMPEQ, CODE_FOR_nothing, "spu_cmpeq", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_CMPEQ_0, CODE_FOR_ceq_v16qi, "spu_cmpeq_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_CMPEQ_1, CODE_FOR_ceq_v16qi, "spu_cmpeq_1", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
|
||||
DEF_BUILTIN (SPU_CMPEQ_2, CODE_FOR_ceq_v8hi, "spu_cmpeq_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_CMPEQ_3, CODE_FOR_ceq_v8hi, "spu_cmpeq_3", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_CMPEQ_4, CODE_FOR_ceq_v4si, "spu_cmpeq_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_CMPEQ_5, CODE_FOR_ceq_v4si, "spu_cmpeq_5", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_CMPEQ_6, CODE_FOR_ceq_v4sf, "spu_cmpeq_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_CMPEQ_7, CODE_FOR_ceq_v16qi, "spu_cmpeq_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTQI))
|
||||
DEF_BUILTIN (SPU_CMPEQ_8, CODE_FOR_ceq_v16qi, "spu_cmpeq_8", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_V16QI, SPU_BTI_INTQI))
|
||||
DEF_BUILTIN (SPU_CMPEQ_9, CODE_FOR_ceq_v8hi, "spu_cmpeq_9", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
|
||||
DEF_BUILTIN (SPU_CMPEQ_10, CODE_FOR_ceq_v8hi, "spu_cmpeq_10", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
|
||||
DEF_BUILTIN (SPU_CMPEQ_11, CODE_FOR_ceq_v4si, "spu_cmpeq_11", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_CMPEQ_12, CODE_FOR_ceq_v4si, "spu_cmpeq_12", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_CMPGT, CODE_FOR_nothing, "spu_cmpgt", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_CMPGT_0, CODE_FOR_clgt_v16qi, "spu_cmpgt_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_CMPGT_1, CODE_FOR_cgt_v16qi, "spu_cmpgt_1", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
|
||||
DEF_BUILTIN (SPU_CMPGT_2, CODE_FOR_clgt_v8hi, "spu_cmpgt_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_CMPGT_3, CODE_FOR_cgt_v8hi, "spu_cmpgt_3", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_CMPGT_4, CODE_FOR_clgt_v4si, "spu_cmpgt_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_CMPGT_5, CODE_FOR_cgt_v4si, "spu_cmpgt_5", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_CMPGT_6, CODE_FOR_cgt_v4sf, "spu_cmpgt_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_CMPGT_7, CODE_FOR_clgt_v16qi, "spu_cmpgt_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTQI))
|
||||
DEF_BUILTIN (SPU_CMPGT_8, CODE_FOR_cgt_v16qi, "spu_cmpgt_8", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_V16QI, SPU_BTI_INTQI))
|
||||
DEF_BUILTIN (SPU_CMPGT_9, CODE_FOR_clgt_v8hi, "spu_cmpgt_9", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
|
||||
DEF_BUILTIN (SPU_CMPGT_10, CODE_FOR_cgt_v8hi, "spu_cmpgt_10", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
|
||||
DEF_BUILTIN (SPU_CMPGT_11, CODE_FOR_cgt_v4si, "spu_cmpgt_11", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_CMPGT_12, CODE_FOR_clgt_v4si, "spu_cmpgt_12", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_HCMPEQ, CODE_FOR_nothing, "spu_hcmpeq", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_HCMPEQ_0, CODE_FOR_spu_heq, "spu_hcmpeq_0", B_INTERNAL, _A3(SPU_BTI_VOID, SPU_BTI_INTSI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_HCMPEQ_1, CODE_FOR_spu_heq, "spu_hcmpeq_1", B_INTERNAL, _A3(SPU_BTI_VOID, SPU_BTI_UINTSI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_HCMPGT, CODE_FOR_nothing, "spu_hcmpgt", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_HCMPGT_0, CODE_FOR_spu_hgt, "spu_hcmpgt_0", B_INTERNAL, _A3(SPU_BTI_VOID, SPU_BTI_INTSI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_HCMPGT_1, CODE_FOR_spu_hlgt, "spu_hcmpgt_1", B_INTERNAL, _A3(SPU_BTI_VOID, SPU_BTI_UINTSI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_CNTB, CODE_FOR_nothing, "spu_cntb", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_CNTB_0, CODE_FOR_cntb_v16qi, "spu_cntb_0", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_V16QI))
|
||||
DEF_BUILTIN (SPU_CNTB_1, CODE_FOR_cntb_v16qi, "spu_cntb_1", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_CNTLZ, CODE_FOR_nothing, "spu_cntlz", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_CNTLZ_0, CODE_FOR_clzv4si2, "spu_cntlz_0", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_CNTLZ_1, CODE_FOR_clzv4si2, "spu_cntlz_1", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_CNTLZ_2, CODE_FOR_clzv4si2, "spu_cntlz_2", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_GATHER, CODE_FOR_nothing, "spu_gather", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_GATHER_0, CODE_FOR_spu_gb, "spu_gather_0", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_GATHER_1, CODE_FOR_spu_gb, "spu_gather_1", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_GATHER_2, CODE_FOR_spu_gbh, "spu_gather_2", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_GATHER_3, CODE_FOR_spu_gbh, "spu_gather_3", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_GATHER_4, CODE_FOR_spu_gbb, "spu_gather_4", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V16QI))
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||||
DEF_BUILTIN (SPU_GATHER_5, CODE_FOR_spu_gbb, "spu_gather_5", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UV16QI))
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||||
DEF_BUILTIN (SPU_GATHER_6, CODE_FOR_spu_gb, "spu_gather_6", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V4SF))
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||||
DEF_BUILTIN (SPU_MASKB, CODE_FOR_nothing, "spu_maskb", B_OVERLOAD, _A1(SPU_BTI_VOID))
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||||
DEF_BUILTIN (SPU_MASKB_0, CODE_FOR_spu_fsmb, "spu_maskb_0", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_UINTHI))
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||||
DEF_BUILTIN (SPU_MASKB_1, CODE_FOR_spu_fsmb, "spu_maskb_1", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_INTHI))
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||||
DEF_BUILTIN (SPU_MASKB_2, CODE_FOR_spu_fsmb, "spu_maskb_2", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_UINTSI))
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||||
DEF_BUILTIN (SPU_MASKB_3, CODE_FOR_spu_fsmb, "spu_maskb_3", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_MASKH, CODE_FOR_nothing, "spu_maskh", B_OVERLOAD, _A1(SPU_BTI_VOID))
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||||
DEF_BUILTIN (SPU_MASKH_0, CODE_FOR_spu_fsmh, "spu_maskh_0", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_UINTQI))
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||||
DEF_BUILTIN (SPU_MASKH_1, CODE_FOR_spu_fsmh, "spu_maskh_1", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_INTQI))
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||||
DEF_BUILTIN (SPU_MASKH_2, CODE_FOR_spu_fsmh, "spu_maskh_2", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_UINTHI))
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||||
DEF_BUILTIN (SPU_MASKH_3, CODE_FOR_spu_fsmh, "spu_maskh_3", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_INTHI))
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||||
DEF_BUILTIN (SPU_MASKH_4, CODE_FOR_spu_fsmh, "spu_maskh_4", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_UINTSI))
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||||
DEF_BUILTIN (SPU_MASKH_5, CODE_FOR_spu_fsmh, "spu_maskh_5", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_MASKW, CODE_FOR_nothing, "spu_maskw", B_OVERLOAD, _A1(SPU_BTI_VOID))
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||||
DEF_BUILTIN (SPU_MASKW_0, CODE_FOR_spu_fsm, "spu_maskw_0", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UINTQI))
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||||
DEF_BUILTIN (SPU_MASKW_1, CODE_FOR_spu_fsm, "spu_maskw_1", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_INTQI))
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||||
DEF_BUILTIN (SPU_MASKW_2, CODE_FOR_spu_fsm, "spu_maskw_2", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UINTHI))
|
||||
DEF_BUILTIN (SPU_MASKW_3, CODE_FOR_spu_fsm, "spu_maskw_3", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_INTHI))
|
||||
DEF_BUILTIN (SPU_MASKW_4, CODE_FOR_spu_fsm, "spu_maskw_4", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UINTSI))
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||||
DEF_BUILTIN (SPU_MASKW_5, CODE_FOR_spu_fsm, "spu_maskw_5", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_SEL, CODE_FOR_nothing, "spu_sel", B_OVERLOAD, _A1(SPU_BTI_VOID))
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||||
DEF_BUILTIN (SPU_SEL_0, CODE_FOR_selb, "spu_sel_0", B_INTERNAL, _A4(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UV2DI))
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||||
DEF_BUILTIN (SPU_SEL_1, CODE_FOR_selb, "spu_sel_1", B_INTERNAL, _A4(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
|
||||
DEF_BUILTIN (SPU_SEL_2, CODE_FOR_selb, "spu_sel_2", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_SEL_3, CODE_FOR_selb, "spu_sel_3", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_SEL_4, CODE_FOR_selb, "spu_sel_4", B_INTERNAL, _A4(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_SEL_5, CODE_FOR_selb, "spu_sel_5", B_INTERNAL, _A4(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_SEL_6, CODE_FOR_selb, "spu_sel_6", B_INTERNAL, _A4(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SEL_7, CODE_FOR_selb, "spu_sel_7", B_INTERNAL, _A4(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SEL_8, CODE_FOR_selb, "spu_sel_8", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_SEL_9, CODE_FOR_selb, "spu_sel_9", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UV2DI))
|
||||
DEF_BUILTIN (SPU_SHUFFLE, CODE_FOR_nothing, "spu_shuffle", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_SHUFFLE_0, CODE_FOR_shufb, "spu_shuffle_0", B_INTERNAL, _A4(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SHUFFLE_1, CODE_FOR_shufb, "spu_shuffle_1", B_INTERNAL, _A4(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SHUFFLE_2, CODE_FOR_shufb, "spu_shuffle_2", B_INTERNAL, _A4(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SHUFFLE_3, CODE_FOR_shufb, "spu_shuffle_3", B_INTERNAL, _A4(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SHUFFLE_4, CODE_FOR_shufb, "spu_shuffle_4", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SHUFFLE_5, CODE_FOR_shufb, "spu_shuffle_5", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SHUFFLE_6, CODE_FOR_shufb, "spu_shuffle_6", B_INTERNAL, _A4(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SHUFFLE_7, CODE_FOR_shufb, "spu_shuffle_7", B_INTERNAL, _A4(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SHUFFLE_8, CODE_FOR_shufb, "spu_shuffle_8", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_SHUFFLE_9, CODE_FOR_shufb, "spu_shuffle_9", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_AND, CODE_FOR_nothing, "spu_and", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_AND_0, CODE_FOR_andv16qi3, "spu_and_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_AND_1, CODE_FOR_andv16qi3, "spu_and_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
|
||||
DEF_BUILTIN (SPU_AND_2, CODE_FOR_andv8hi3, "spu_and_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_AND_3, CODE_FOR_andv8hi3, "spu_and_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_AND_4, CODE_FOR_andv4si3, "spu_and_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_AND_5, CODE_FOR_andv4si3, "spu_and_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_AND_6, CODE_FOR_andv2di3, "spu_and_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
|
||||
DEF_BUILTIN (SPU_AND_7, CODE_FOR_andv2di3, "spu_and_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
|
||||
DEF_BUILTIN (SPU_AND_8, CODE_FOR_andv4si3, "spu_and_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_AND_9, CODE_FOR_andv2di3, "spu_and_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_AND_10, CODE_FOR_andv16qi3, "spu_and_10", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTQI))
|
||||
DEF_BUILTIN (SPU_AND_11, CODE_FOR_andv16qi3, "spu_and_11", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTQI))
|
||||
DEF_BUILTIN (SPU_AND_12, CODE_FOR_andv8hi3, "spu_and_12", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
|
||||
DEF_BUILTIN (SPU_AND_13, CODE_FOR_andv8hi3, "spu_and_13", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
|
||||
DEF_BUILTIN (SPU_AND_14, CODE_FOR_andv4si3, "spu_and_14", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_AND_15, CODE_FOR_andv4si3, "spu_and_15", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_ANDC, CODE_FOR_nothing, "spu_andc", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_ANDC_0, CODE_FOR_andc_v2di, "spu_andc_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
|
||||
DEF_BUILTIN (SPU_ANDC_1, CODE_FOR_andc_v2di, "spu_andc_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
|
||||
DEF_BUILTIN (SPU_ANDC_2, CODE_FOR_andc_v4si, "spu_andc_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_ANDC_3, CODE_FOR_andc_v4si, "spu_andc_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_ANDC_4, CODE_FOR_andc_v8hi, "spu_andc_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_ANDC_5, CODE_FOR_andc_v8hi, "spu_andc_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_ANDC_6, CODE_FOR_andc_v16qi, "spu_andc_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
|
||||
DEF_BUILTIN (SPU_ANDC_7, CODE_FOR_andc_v16qi, "spu_andc_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_ANDC_8, CODE_FOR_andc_v4si, "spu_andc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_ANDC_9, CODE_FOR_andc_v2di, "spu_andc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_EQV, CODE_FOR_nothing, "spu_eqv", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_EQV_0, CODE_FOR_eqv_v2di, "spu_eqv_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
|
||||
DEF_BUILTIN (SPU_EQV_1, CODE_FOR_eqv_v2di, "spu_eqv_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
|
||||
DEF_BUILTIN (SPU_EQV_2, CODE_FOR_eqv_v4si, "spu_eqv_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_EQV_3, CODE_FOR_eqv_v4si, "spu_eqv_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_EQV_4, CODE_FOR_eqv_v8hi, "spu_eqv_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_EQV_5, CODE_FOR_eqv_v8hi, "spu_eqv_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_EQV_6, CODE_FOR_eqv_v16qi, "spu_eqv_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
|
||||
DEF_BUILTIN (SPU_EQV_7, CODE_FOR_eqv_v16qi, "spu_eqv_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_EQV_8, CODE_FOR_eqv_v4si, "spu_eqv_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_EQV_9, CODE_FOR_eqv_v2di, "spu_eqv_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_NAND, CODE_FOR_nothing, "spu_nand", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_NAND_0, CODE_FOR_nand_v2di, "spu_nand_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
|
||||
DEF_BUILTIN (SPU_NAND_1, CODE_FOR_nand_v2di, "spu_nand_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
|
||||
DEF_BUILTIN (SPU_NAND_2, CODE_FOR_nand_v4si, "spu_nand_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_NAND_3, CODE_FOR_nand_v4si, "spu_nand_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_NAND_4, CODE_FOR_nand_v8hi, "spu_nand_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_NAND_5, CODE_FOR_nand_v8hi, "spu_nand_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_NAND_6, CODE_FOR_nand_v16qi, "spu_nand_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
|
||||
DEF_BUILTIN (SPU_NAND_7, CODE_FOR_nand_v16qi, "spu_nand_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
|
||||
DEF_BUILTIN (SPU_NAND_8, CODE_FOR_nand_v4si, "spu_nand_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
|
||||
DEF_BUILTIN (SPU_NAND_9, CODE_FOR_nand_v2di, "spu_nand_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
|
||||
DEF_BUILTIN (SPU_NOR, CODE_FOR_nothing, "spu_nor", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_NOR_0, CODE_FOR_nor_v2di, "spu_nor_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
|
||||
DEF_BUILTIN (SPU_NOR_1, CODE_FOR_nor_v2di, "spu_nor_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
|
||||
DEF_BUILTIN (SPU_NOR_2, CODE_FOR_nor_v4si, "spu_nor_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_NOR_3, CODE_FOR_nor_v4si, "spu_nor_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
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DEF_BUILTIN (SPU_NOR_4, CODE_FOR_nor_v8hi, "spu_nor_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
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DEF_BUILTIN (SPU_NOR_5, CODE_FOR_nor_v8hi, "spu_nor_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
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DEF_BUILTIN (SPU_NOR_6, CODE_FOR_nor_v16qi, "spu_nor_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
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DEF_BUILTIN (SPU_NOR_7, CODE_FOR_nor_v16qi, "spu_nor_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
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DEF_BUILTIN (SPU_NOR_8, CODE_FOR_nor_v4si, "spu_nor_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
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DEF_BUILTIN (SPU_NOR_9, CODE_FOR_nor_v2di, "spu_nor_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
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DEF_BUILTIN (SPU_OR, CODE_FOR_nothing, "spu_or", B_OVERLOAD, _A1(SPU_BTI_VOID))
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DEF_BUILTIN (SPU_OR_0, CODE_FOR_iorv16qi3, "spu_or_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
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DEF_BUILTIN (SPU_OR_1, CODE_FOR_iorv16qi3, "spu_or_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
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DEF_BUILTIN (SPU_OR_2, CODE_FOR_iorv8hi3, "spu_or_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
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DEF_BUILTIN (SPU_OR_3, CODE_FOR_iorv8hi3, "spu_or_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
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DEF_BUILTIN (SPU_OR_4, CODE_FOR_iorv4si3, "spu_or_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
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DEF_BUILTIN (SPU_OR_5, CODE_FOR_iorv4si3, "spu_or_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
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DEF_BUILTIN (SPU_OR_6, CODE_FOR_iorv2di3, "spu_or_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
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DEF_BUILTIN (SPU_OR_7, CODE_FOR_iorv2di3, "spu_or_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
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DEF_BUILTIN (SPU_OR_8, CODE_FOR_iorv4si3, "spu_or_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
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DEF_BUILTIN (SPU_OR_9, CODE_FOR_iorv2di3, "spu_or_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
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DEF_BUILTIN (SPU_OR_10, CODE_FOR_iorv16qi3, "spu_or_10", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTQI))
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DEF_BUILTIN (SPU_OR_11, CODE_FOR_iorv16qi3, "spu_or_11", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTQI))
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DEF_BUILTIN (SPU_OR_12, CODE_FOR_iorv8hi3, "spu_or_12", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
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DEF_BUILTIN (SPU_OR_13, CODE_FOR_iorv8hi3, "spu_or_13", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
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DEF_BUILTIN (SPU_OR_14, CODE_FOR_iorv4si3, "spu_or_14", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
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DEF_BUILTIN (SPU_OR_15, CODE_FOR_iorv4si3, "spu_or_15", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
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DEF_BUILTIN (SPU_ORC, CODE_FOR_nothing, "spu_orc", B_OVERLOAD, _A1(SPU_BTI_VOID))
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DEF_BUILTIN (SPU_ORC_0, CODE_FOR_orc_v2di, "spu_orc_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
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DEF_BUILTIN (SPU_ORC_1, CODE_FOR_orc_v2di, "spu_orc_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
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DEF_BUILTIN (SPU_ORC_2, CODE_FOR_orc_v4si, "spu_orc_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
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DEF_BUILTIN (SPU_ORC_3, CODE_FOR_orc_v4si, "spu_orc_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
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DEF_BUILTIN (SPU_ORC_4, CODE_FOR_orc_v8hi, "spu_orc_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
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DEF_BUILTIN (SPU_ORC_5, CODE_FOR_orc_v8hi, "spu_orc_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
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DEF_BUILTIN (SPU_ORC_6, CODE_FOR_orc_v16qi, "spu_orc_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
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DEF_BUILTIN (SPU_ORC_7, CODE_FOR_orc_v16qi, "spu_orc_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
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DEF_BUILTIN (SPU_ORC_8, CODE_FOR_orc_v4si, "spu_orc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
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DEF_BUILTIN (SPU_ORC_9, CODE_FOR_orc_v2di, "spu_orc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
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DEF_BUILTIN (SPU_ORX, CODE_FOR_nothing, "spu_orx", B_OVERLOAD, _A1(SPU_BTI_VOID))
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DEF_BUILTIN (SPU_ORX_0, CODE_FOR_spu_orx, "spu_orx_0", B_INTERNAL, _A2(SPU_BTI_V4SI, SPU_BTI_V4SI))
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DEF_BUILTIN (SPU_ORX_1, CODE_FOR_spu_orx, "spu_orx_1", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UV4SI))
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DEF_BUILTIN (SPU_XOR, CODE_FOR_nothing, "spu_xor", B_OVERLOAD, _A1(SPU_BTI_VOID))
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DEF_BUILTIN (SPU_XOR_0, CODE_FOR_xorv16qi3, "spu_xor_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
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||||
DEF_BUILTIN (SPU_XOR_1, CODE_FOR_xorv16qi3, "spu_xor_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
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||||
DEF_BUILTIN (SPU_XOR_2, CODE_FOR_xorv8hi3, "spu_xor_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
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DEF_BUILTIN (SPU_XOR_3, CODE_FOR_xorv8hi3, "spu_xor_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
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DEF_BUILTIN (SPU_XOR_4, CODE_FOR_xorv4si3, "spu_xor_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
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DEF_BUILTIN (SPU_XOR_5, CODE_FOR_xorv4si3, "spu_xor_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
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DEF_BUILTIN (SPU_XOR_6, CODE_FOR_xorv2di3, "spu_xor_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
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DEF_BUILTIN (SPU_XOR_7, CODE_FOR_xorv2di3, "spu_xor_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
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DEF_BUILTIN (SPU_XOR_8, CODE_FOR_xorv4si3, "spu_xor_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
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DEF_BUILTIN (SPU_XOR_9, CODE_FOR_xorv2di3, "spu_xor_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
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DEF_BUILTIN (SPU_XOR_10, CODE_FOR_xorv16qi3, "spu_xor_10", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTQI))
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DEF_BUILTIN (SPU_XOR_11, CODE_FOR_xorv16qi3, "spu_xor_11", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTQI))
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DEF_BUILTIN (SPU_XOR_12, CODE_FOR_xorv8hi3, "spu_xor_12", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
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DEF_BUILTIN (SPU_XOR_13, CODE_FOR_xorv8hi3, "spu_xor_13", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
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DEF_BUILTIN (SPU_XOR_14, CODE_FOR_xorv4si3, "spu_xor_14", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
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DEF_BUILTIN (SPU_XOR_15, CODE_FOR_xorv4si3, "spu_xor_15", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
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DEF_BUILTIN (SPU_RL, CODE_FOR_nothing, "spu_rl", B_OVERLOAD, _A1(SPU_BTI_VOID))
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DEF_BUILTIN (SPU_RL_0, CODE_FOR_rotlv8hi3, "spu_rl_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_V8HI))
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DEF_BUILTIN (SPU_RL_1, CODE_FOR_rotlv8hi3, "spu_rl_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
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DEF_BUILTIN (SPU_RL_2, CODE_FOR_rotlv4si3, "spu_rl_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_V4SI))
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DEF_BUILTIN (SPU_RL_3, CODE_FOR_rotlv4si3, "spu_rl_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
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DEF_BUILTIN (SPU_RL_4, CODE_FOR_rotlv8hi3, "spu_rl_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTHI))
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DEF_BUILTIN (SPU_RL_5, CODE_FOR_rotlv8hi3, "spu_rl_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
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||||
DEF_BUILTIN (SPU_RL_6, CODE_FOR_rotlv4si3, "spu_rl_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RL_7, CODE_FOR_rotlv4si3, "spu_rl_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
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DEF_BUILTIN (SPU_RLQW, CODE_FOR_nothing, "spu_rlqw", B_OVERLOAD, _A1(SPU_BTI_VOID))
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DEF_BUILTIN (SPU_RLQW_0, CODE_FOR_rotqbi_ti, "spu_rlqw_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
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DEF_BUILTIN (SPU_RLQW_1, CODE_FOR_rotqbi_ti, "spu_rlqw_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
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DEF_BUILTIN (SPU_RLQW_2, CODE_FOR_rotqbi_ti, "spu_rlqw_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
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DEF_BUILTIN (SPU_RLQW_3, CODE_FOR_rotqbi_ti, "spu_rlqw_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
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DEF_BUILTIN (SPU_RLQW_4, CODE_FOR_rotqbi_ti, "spu_rlqw_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQW_5, CODE_FOR_rotqbi_ti, "spu_rlqw_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQW_6, CODE_FOR_rotqbi_ti, "spu_rlqw_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQW_7, CODE_FOR_rotqbi_ti, "spu_rlqw_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQW_8, CODE_FOR_rotqbi_ti, "spu_rlqw_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQW_9, CODE_FOR_rotqbi_ti, "spu_rlqw_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQWBYTE, CODE_FOR_nothing, "spu_rlqwbyte", B_OVERLOAD, _A1(SPU_BTI_VOID))
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||||
DEF_BUILTIN (SPU_RLQWBYTE_0, CODE_FOR_rotqby_ti, "spu_rlqwbyte_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQWBYTE_1, CODE_FOR_rotqby_ti, "spu_rlqwbyte_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQWBYTE_2, CODE_FOR_rotqby_ti, "spu_rlqwbyte_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQWBYTE_3, CODE_FOR_rotqby_ti, "spu_rlqwbyte_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQWBYTE_4, CODE_FOR_rotqby_ti, "spu_rlqwbyte_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQWBYTE_5, CODE_FOR_rotqby_ti, "spu_rlqwbyte_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQWBYTE_6, CODE_FOR_rotqby_ti, "spu_rlqwbyte_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLQWBYTE_7, CODE_FOR_rotqby_ti, "spu_rlqwbyte_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQWBYTE_8, CODE_FOR_rotqby_ti, "spu_rlqwbyte_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLQWBYTE_9, CODE_FOR_rotqby_ti, "spu_rlqwbyte_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
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||||
DEF_BUILTIN (SPU_RLQWBYTEBC, CODE_FOR_nothing, "spu_rlqwbytebc", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_RLQWBYTEBC_0, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLQWBYTEBC_1, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLQWBYTEBC_2, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLQWBYTEBC_3, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLQWBYTEBC_4, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLQWBYTEBC_5, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLQWBYTEBC_6, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLQWBYTEBC_7, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLQWBYTEBC_8, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLQWBYTEBC_9, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASK, CODE_FOR_nothing, "spu_rlmask", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_RLMASK_0, CODE_FOR_rotm_v8hi, "spu_rlmask_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_RLMASK_1, CODE_FOR_rotm_v8hi, "spu_rlmask_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_RLMASK_2, CODE_FOR_rotm_v4si, "spu_rlmask_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_RLMASK_3, CODE_FOR_rotm_v4si, "spu_rlmask_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_RLMASK_4, CODE_FOR_rotm_v8hi, "spu_rlmask_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASK_5, CODE_FOR_rotm_v8hi, "spu_rlmask_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASK_6, CODE_FOR_rotm_v4si, "spu_rlmask_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASK_7, CODE_FOR_rotm_v4si, "spu_rlmask_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKA, CODE_FOR_nothing, "spu_rlmaska", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_RLMASKA_0, CODE_FOR_rotma_v8hi, "spu_rlmaska_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_RLMASKA_1, CODE_FOR_rotma_v8hi, "spu_rlmaska_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
|
||||
DEF_BUILTIN (SPU_RLMASKA_2, CODE_FOR_rotma_v4si, "spu_rlmaska_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_RLMASKA_3, CODE_FOR_rotma_v4si, "spu_rlmaska_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
|
||||
DEF_BUILTIN (SPU_RLMASKA_4, CODE_FOR_rotma_v8hi, "spu_rlmaska_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKA_5, CODE_FOR_rotma_v8hi, "spu_rlmaska_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKA_6, CODE_FOR_rotma_v4si, "spu_rlmaska_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKA_7, CODE_FOR_rotma_v4si, "spu_rlmaska_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQW, CODE_FOR_nothing, "spu_rlmaskqw", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_RLMASKQW_0, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQW_1, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQW_2, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQW_3, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQW_4, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQW_5, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQW_6, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQW_7, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQW_8, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQW_9, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTE, CODE_FOR_nothing, "spu_rlmaskqwbyte", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTE_0, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTE_1, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTE_2, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTE_3, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTE_4, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTE_5, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTE_6, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTE_7, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTE_8, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTE_9, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTEBC, CODE_FOR_nothing, "spu_rlmaskqwbytebc", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_0, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_1, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_2, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_3, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_4, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_5, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_6, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_7, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_8, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_9, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_SL, CODE_FOR_nothing, "spu_sl", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_SL_0, CODE_FOR_ashlv8hi3, "spu_sl_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_SL_1, CODE_FOR_ashlv8hi3, "spu_sl_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV8HI))
|
||||
DEF_BUILTIN (SPU_SL_2, CODE_FOR_ashlv4si3, "spu_sl_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_SL_3, CODE_FOR_ashlv4si3, "spu_sl_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV4SI))
|
||||
DEF_BUILTIN (SPU_SL_4, CODE_FOR_ashlv8hi3, "spu_sl_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SL_5, CODE_FOR_ashlv8hi3, "spu_sl_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SL_6, CODE_FOR_ashlv4si3, "spu_sl_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SL_7, CODE_FOR_ashlv4si3, "spu_sl_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQW, CODE_FOR_nothing, "spu_slqw", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_SLQW_0, CODE_FOR_shlqbi_ti, "spu_slqw_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQW_1, CODE_FOR_shlqbi_ti, "spu_slqw_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQW_2, CODE_FOR_shlqbi_ti, "spu_slqw_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQW_3, CODE_FOR_shlqbi_ti, "spu_slqw_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQW_4, CODE_FOR_shlqbi_ti, "spu_slqw_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQW_5, CODE_FOR_shlqbi_ti, "spu_slqw_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQW_6, CODE_FOR_shlqbi_ti, "spu_slqw_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQW_7, CODE_FOR_shlqbi_ti, "spu_slqw_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQW_8, CODE_FOR_shlqbi_ti, "spu_slqw_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQW_9, CODE_FOR_shlqbi_ti, "spu_slqw_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTE, CODE_FOR_nothing, "spu_slqwbyte", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_SLQWBYTE_0, CODE_FOR_shlqby_ti, "spu_slqwbyte_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTE_1, CODE_FOR_shlqby_ti, "spu_slqwbyte_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTE_2, CODE_FOR_shlqby_ti, "spu_slqwbyte_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTE_3, CODE_FOR_shlqby_ti, "spu_slqwbyte_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTE_4, CODE_FOR_shlqby_ti, "spu_slqwbyte_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTE_5, CODE_FOR_shlqby_ti, "spu_slqwbyte_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTE_6, CODE_FOR_shlqby_ti, "spu_slqwbyte_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTE_7, CODE_FOR_shlqby_ti, "spu_slqwbyte_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTE_8, CODE_FOR_shlqby_ti, "spu_slqwbyte_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTE_9, CODE_FOR_shlqby_ti, "spu_slqwbyte_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTEBC, CODE_FOR_nothing, "spu_slqwbytebc", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_SLQWBYTEBC_0, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTEBC_1, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTEBC_2, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTEBC_3, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTEBC_4, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTEBC_5, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTEBC_6, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTEBC_7, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTEBC_8, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SLQWBYTEBC_9, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
|
||||
|
||||
DEF_BUILTIN (SPU_SPLATS, CODE_FOR_nothing, "spu_splats", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_SPLATS_0, CODE_FOR_spu_splats, "spu_splats_0", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_UINTQI))
|
||||
DEF_BUILTIN (SPU_SPLATS_1, CODE_FOR_spu_splats, "spu_splats_1", B_INTERNAL, _A2(SPU_BTI_V16QI, SPU_BTI_INTQI))
|
||||
DEF_BUILTIN (SPU_SPLATS_2, CODE_FOR_spu_splats, "spu_splats_2", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_UINTHI))
|
||||
DEF_BUILTIN (SPU_SPLATS_3, CODE_FOR_spu_splats, "spu_splats_3", B_INTERNAL, _A2(SPU_BTI_V8HI, SPU_BTI_INTHI))
|
||||
DEF_BUILTIN (SPU_SPLATS_4, CODE_FOR_spu_splats, "spu_splats_4", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UINTSI))
|
||||
DEF_BUILTIN (SPU_SPLATS_5, CODE_FOR_spu_splats, "spu_splats_5", B_INTERNAL, _A2(SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_SPLATS_6, CODE_FOR_spu_splats, "spu_splats_6", B_INTERNAL, _A2(SPU_BTI_UV2DI, SPU_BTI_UINTDI))
|
||||
DEF_BUILTIN (SPU_SPLATS_7, CODE_FOR_spu_splats, "spu_splats_7", B_INTERNAL, _A2(SPU_BTI_V2DI, SPU_BTI_INTDI))
|
||||
DEF_BUILTIN (SPU_SPLATS_8, CODE_FOR_spu_splats, "spu_splats_8", B_INTERNAL, _A2(SPU_BTI_V4SF, SPU_BTI_FLOAT))
|
||||
DEF_BUILTIN (SPU_SPLATS_9, CODE_FOR_spu_splats, "spu_splats_9", B_INTERNAL, _A2(SPU_BTI_V2DF, SPU_BTI_DOUBLE))
|
||||
DEF_BUILTIN (SPU_EXTRACT, CODE_FOR_nothing, "spu_extract", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_EXTRACT_0, CODE_FOR_spu_extract, "spu_extract_0", B_INTERNAL, _A3(SPU_BTI_UINTQI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_EXTRACT_1, CODE_FOR_spu_extract, "spu_extract_1", B_INTERNAL, _A3(SPU_BTI_INTQI, SPU_BTI_V16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_EXTRACT_2, CODE_FOR_spu_extract, "spu_extract_2", B_INTERNAL, _A3(SPU_BTI_UINTHI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_EXTRACT_3, CODE_FOR_spu_extract, "spu_extract_3", B_INTERNAL, _A3(SPU_BTI_INTHI, SPU_BTI_V8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_EXTRACT_4, CODE_FOR_spu_extract, "spu_extract_4", B_INTERNAL, _A3(SPU_BTI_UINTSI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_EXTRACT_5, CODE_FOR_spu_extract, "spu_extract_5", B_INTERNAL, _A3(SPU_BTI_INTSI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_EXTRACT_6, CODE_FOR_spu_extract, "spu_extract_6", B_INTERNAL, _A3(SPU_BTI_UINTDI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_EXTRACT_7, CODE_FOR_spu_extract, "spu_extract_7", B_INTERNAL, _A3(SPU_BTI_INTDI, SPU_BTI_V2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_EXTRACT_8, CODE_FOR_spu_extract, "spu_extract_8", B_INTERNAL, _A3(SPU_BTI_FLOAT, SPU_BTI_V4SF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_EXTRACT_9, CODE_FOR_spu_extract, "spu_extract_9", B_INTERNAL, _A3(SPU_BTI_DOUBLE, SPU_BTI_V2DF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_INSERT, CODE_FOR_nothing, "spu_insert", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_INSERT_0, CODE_FOR_spu_insert, "spu_insert_0", B_INTERNAL, _A4(SPU_BTI_UV16QI, SPU_BTI_UINTQI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_INSERT_1, CODE_FOR_spu_insert, "spu_insert_1", B_INTERNAL, _A4(SPU_BTI_V16QI, SPU_BTI_INTQI, SPU_BTI_V16QI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_INSERT_2, CODE_FOR_spu_insert, "spu_insert_2", B_INTERNAL, _A4(SPU_BTI_UV8HI, SPU_BTI_UINTHI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_INSERT_3, CODE_FOR_spu_insert, "spu_insert_3", B_INTERNAL, _A4(SPU_BTI_V8HI, SPU_BTI_INTHI, SPU_BTI_V8HI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_INSERT_4, CODE_FOR_spu_insert, "spu_insert_4", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UINTSI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_INSERT_5, CODE_FOR_spu_insert, "spu_insert_5", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_INTSI, SPU_BTI_V4SI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_INSERT_6, CODE_FOR_spu_insert, "spu_insert_6", B_INTERNAL, _A4(SPU_BTI_UV2DI, SPU_BTI_UINTDI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_INSERT_7, CODE_FOR_spu_insert, "spu_insert_7", B_INTERNAL, _A4(SPU_BTI_V2DI, SPU_BTI_INTDI, SPU_BTI_V2DI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_INSERT_8, CODE_FOR_spu_insert, "spu_insert_8", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_FLOAT, SPU_BTI_V4SF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_INSERT_9, CODE_FOR_spu_insert, "spu_insert_9", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_DOUBLE, SPU_BTI_V2DF, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_PROMOTE, CODE_FOR_nothing, "spu_promote", B_OVERLOAD, _A1(SPU_BTI_VOID))
|
||||
DEF_BUILTIN (SPU_PROMOTE_0, CODE_FOR_spu_promote, "spu_promote_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UINTQI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_PROMOTE_1, CODE_FOR_spu_promote, "spu_promote_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_INTQI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_PROMOTE_2, CODE_FOR_spu_promote, "spu_promote_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UINTHI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_PROMOTE_3, CODE_FOR_spu_promote, "spu_promote_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_INTHI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_PROMOTE_4, CODE_FOR_spu_promote, "spu_promote_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UINTSI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_PROMOTE_5, CODE_FOR_spu_promote, "spu_promote_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_INTSI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_PROMOTE_6, CODE_FOR_spu_promote, "spu_promote_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UINTDI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_PROMOTE_7, CODE_FOR_spu_promote, "spu_promote_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_INTDI, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_PROMOTE_8, CODE_FOR_spu_promote, "spu_promote_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_FLOAT, SPU_BTI_INTSI))
|
||||
DEF_BUILTIN (SPU_PROMOTE_9, CODE_FOR_spu_promote, "spu_promote_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_DOUBLE, SPU_BTI_INTSI))
|
||||
|
||||
/* We need something that is not B_INTERNAL as a sentinal. */
|
||||
|
||||
/* These are for the convenience of imlpemnting fma() in the standard
|
||||
libraries. */
|
||||
DEF_BUILTIN (SCALAR_FMA, CODE_FOR_fma_sf, "fmas", B_INSN, _A4(SPU_BTI_FLOAT, SPU_BTI_FLOAT, SPU_BTI_FLOAT, SPU_BTI_FLOAT))
|
||||
DEF_BUILTIN (SCALAR_DFMA, CODE_FOR_fma_df, "dfmas", B_INSN, _A4(SPU_BTI_DOUBLE, SPU_BTI_DOUBLE, SPU_BTI_DOUBLE, SPU_BTI_DOUBLE))
|
||||
|
||||
DEF_BUILTIN (SPU_ALIGN_HINT, CODE_FOR_spu_align_hint,"spu_align_hint", B_INSN, _A4(SPU_BTI_VOID, SPU_BTI_PTR, SPU_BTI_7, SPU_BTI_7))
|
||||
#undef _A1
|
||||
#undef _A2
|
||||
#undef _A3
|
||||
#undef _A4
|
||||
120
gcc/config/spu/spu-builtins.h
Normal file
120
gcc/config/spu/spu-builtins.h
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
/* built-ins */
|
||||
|
||||
enum spu_builtin_type_index
|
||||
{
|
||||
SPU_BTI_END_OF_PARAMS,
|
||||
|
||||
/* We create new type nodes for these. */
|
||||
SPU_BTI_V16QI,
|
||||
SPU_BTI_V8HI,
|
||||
SPU_BTI_V4SI,
|
||||
SPU_BTI_V2DI,
|
||||
SPU_BTI_V4SF,
|
||||
SPU_BTI_V2DF,
|
||||
SPU_BTI_UV16QI,
|
||||
SPU_BTI_UV8HI,
|
||||
SPU_BTI_UV4SI,
|
||||
SPU_BTI_UV2DI,
|
||||
|
||||
/* A 16-byte type. (Implemented with V16QI_type_node) */
|
||||
SPU_BTI_QUADWORD,
|
||||
|
||||
/* These all correspond to intSI_type_node */
|
||||
SPU_BTI_7,
|
||||
SPU_BTI_S7,
|
||||
SPU_BTI_U7,
|
||||
SPU_BTI_S10,
|
||||
SPU_BTI_S10_4,
|
||||
SPU_BTI_U14,
|
||||
SPU_BTI_16,
|
||||
SPU_BTI_S16,
|
||||
SPU_BTI_S16_2,
|
||||
SPU_BTI_U16,
|
||||
SPU_BTI_U16_2,
|
||||
SPU_BTI_U18,
|
||||
|
||||
/* These correspond to the standard types */
|
||||
SPU_BTI_INTQI,
|
||||
SPU_BTI_INTHI,
|
||||
SPU_BTI_INTSI,
|
||||
SPU_BTI_INTDI,
|
||||
|
||||
SPU_BTI_UINTQI,
|
||||
SPU_BTI_UINTHI,
|
||||
SPU_BTI_UINTSI,
|
||||
SPU_BTI_UINTDI,
|
||||
|
||||
SPU_BTI_FLOAT,
|
||||
SPU_BTI_DOUBLE,
|
||||
|
||||
SPU_BTI_VOID,
|
||||
SPU_BTI_PTR,
|
||||
|
||||
SPU_BTI_MAX
|
||||
};
|
||||
|
||||
#define V16QI_type_node (spu_builtin_types[SPU_BTI_V16QI])
|
||||
#define V8HI_type_node (spu_builtin_types[SPU_BTI_V8HI])
|
||||
#define V4SI_type_node (spu_builtin_types[SPU_BTI_V4SI])
|
||||
#define V2DI_type_node (spu_builtin_types[SPU_BTI_V2DI])
|
||||
#define V4SF_type_node (spu_builtin_types[SPU_BTI_V4SF])
|
||||
#define V2DF_type_node (spu_builtin_types[SPU_BTI_V2DF])
|
||||
#define unsigned_V16QI_type_node (spu_builtin_types[SPU_BTI_UV16QI])
|
||||
#define unsigned_V8HI_type_node (spu_builtin_types[SPU_BTI_UV8HI])
|
||||
#define unsigned_V4SI_type_node (spu_builtin_types[SPU_BTI_UV4SI])
|
||||
#define unsigned_V2DI_type_node (spu_builtin_types[SPU_BTI_UV2DI])
|
||||
|
||||
extern GTY(()) tree spu_builtin_types[SPU_BTI_MAX];
|
||||
|
||||
/* Some builtins require special handling. This enum differentiates. */
|
||||
enum spu_builtin_type {
|
||||
B_INSN,
|
||||
B_JUMP,
|
||||
B_BISLED,
|
||||
B_CALL,
|
||||
B_HINT,
|
||||
B_OVERLOAD,
|
||||
B_INTERNAL
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
#define DEF_BUILTIN(fcode, icode, name, type, params) fcode,
|
||||
#include "spu-builtins.def"
|
||||
#undef DEF_BUILTIN
|
||||
NUM_SPU_BUILTINS
|
||||
} spu_function_code;
|
||||
|
||||
struct spu_builtin_description {
|
||||
spu_function_code fcode;
|
||||
enum insn_code icode;
|
||||
const char *name;
|
||||
enum spu_builtin_type type;
|
||||
|
||||
/* The first element of parm is always the return type. The rest
|
||||
* are a zero terminated list of parameters. */
|
||||
int parm[5];
|
||||
|
||||
tree fndecl;
|
||||
};
|
||||
|
||||
extern GTY(()) struct spu_builtin_description spu_builtins[];
|
||||
|
||||
|
||||
|
||||
872
gcc/config/spu/spu-builtins.md
Normal file
872
gcc/config/spu/spu-builtins.md
Normal file
|
|
@ -0,0 +1,872 @@
|
|||
;; Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
;; This file is free software; you can redistribute it and/or modify it under
|
||||
;; the terms of the GNU General Public License as published by the Free
|
||||
;; Software Foundation; either version 2 of the License, or (at your option)
|
||||
;; any later version.
|
||||
|
||||
;; This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
;; for more details.
|
||||
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with this file; see the file COPYING. If not, write to the Free
|
||||
;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
;; 02110-1301, USA.
|
||||
|
||||
|
||||
;; This includes expands for all the intrinsics.
|
||||
;; spu_expand_builtin looks at the mode of match_operand.
|
||||
|
||||
|
||||
;; load/store
|
||||
|
||||
(define_expand "spu_lqd"
|
||||
[(set (match_operand:TI 0 "spu_reg_operand" "")
|
||||
(mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
|
||||
(match_operand:SI 2 "spu_nonmem_operand" ""))
|
||||
(const_int -16))))]
|
||||
""
|
||||
{
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& (INTVAL (operands[2]) & 15) != 0)
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
|
||||
if (GET_CODE (operands[2]) != CONST_INT)
|
||||
{
|
||||
rtx op2 = operands[2];
|
||||
operands[2] = force_reg (Pmode, operands[2]);
|
||||
if (!ALIGNED_SYMBOL_REF_P (op2))
|
||||
emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16)));
|
||||
}
|
||||
})
|
||||
|
||||
(define_expand "spu_lqx"
|
||||
[(set (match_operand:TI 0 "spu_reg_operand" "")
|
||||
(mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
|
||||
(match_operand:SI 2 "spu_reg_operand" ""))
|
||||
(const_int -16))))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "spu_lqa"
|
||||
[(set (match_operand:TI 0 "spu_reg_operand" "")
|
||||
(mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "")
|
||||
(const_int -16))))]
|
||||
""
|
||||
{
|
||||
if (GET_CODE (operands[1]) == CONST_INT
|
||||
&& (INTVAL (operands[1]) & 15) != 0)
|
||||
operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
|
||||
})
|
||||
|
||||
(define_expand "spu_lqr"
|
||||
[(set (match_operand:TI 0 "spu_reg_operand" "")
|
||||
(mem:TI (and:SI (match_operand:SI 1 "address_operand" "")
|
||||
(const_int -16))))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "spu_stqd"
|
||||
[(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
|
||||
(match_operand:SI 2 "spu_nonmem_operand" ""))
|
||||
(const_int -16)))
|
||||
(match_operand:TI 0 "spu_reg_operand" "r,r"))]
|
||||
""
|
||||
{
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& (INTVAL (operands[2]) & 15) != 0)
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
|
||||
if (GET_CODE (operands[2]) != CONST_INT)
|
||||
{
|
||||
rtx op2 = operands[2];
|
||||
operands[2] = force_reg (Pmode, operands[2]);
|
||||
if (!ALIGNED_SYMBOL_REF_P (op2))
|
||||
emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16)));
|
||||
}
|
||||
})
|
||||
|
||||
(define_expand "spu_stqx"
|
||||
[(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
|
||||
(match_operand:SI 2 "spu_reg_operand" ""))
|
||||
(const_int -16)))
|
||||
(match_operand:TI 0 "spu_reg_operand" "r"))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "spu_stqa"
|
||||
[(set (mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "")
|
||||
(const_int -16)))
|
||||
(match_operand:TI 0 "spu_reg_operand" "r"))]
|
||||
""
|
||||
{
|
||||
if (GET_CODE (operands[1]) == CONST_INT
|
||||
&& (INTVAL (operands[1]) & 15) != 0)
|
||||
operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
|
||||
})
|
||||
|
||||
(define_expand "spu_stqr"
|
||||
[(set (mem:TI (and:SI (match_operand:SI 1 "address_operand" "")
|
||||
(const_int -16)))
|
||||
(match_operand:TI 0 "spu_reg_operand" ""))]
|
||||
""
|
||||
"")
|
||||
|
||||
|
||||
;; generate control word
|
||||
|
||||
(define_expand "spu_cbx"
|
||||
[(set (match_operand:TI 0 "spu_reg_operand" "")
|
||||
(unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
|
||||
(match_operand:SI 2 "spu_nonmem_operand" "")
|
||||
(const_int 1)] UNSPEC_CPAT))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "spu_chx"
|
||||
[(set (match_operand:TI 0 "spu_reg_operand" "")
|
||||
(unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
|
||||
(match_operand:SI 2 "spu_nonmem_operand" "")
|
||||
(const_int 2)] UNSPEC_CPAT))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "spu_cwx"
|
||||
[(set (match_operand:TI 0 "spu_reg_operand" "")
|
||||
(unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
|
||||
(match_operand:SI 2 "spu_nonmem_operand" "")
|
||||
(const_int 4)] UNSPEC_CPAT))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "spu_cdx"
|
||||
[(set (match_operand:TI 0 "spu_reg_operand" "")
|
||||
(unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
|
||||
(match_operand:SI 2 "spu_nonmem_operand" "")
|
||||
(const_int 8)] UNSPEC_CPAT))]
|
||||
""
|
||||
"")
|
||||
|
||||
|
||||
|
||||
;; Constant formation
|
||||
|
||||
(define_expand "spu_ilhu"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
|
||||
(const_vector:V4SI [(match_operand:SI 1 "immediate_operand" "")]))]
|
||||
""
|
||||
"{ emit_insn(gen_movv4si(operands[0], spu_const(V4SImode, (INTVAL(operands[1]) << 16))));
|
||||
DONE;
|
||||
}")
|
||||
|
||||
|
||||
;; integer subtract
|
||||
(define_expand "spu_sfh"
|
||||
[(set (match_operand:V8HI 0 "spu_reg_operand" "")
|
||||
(minus:V8HI (match_operand:V8HI 2 "spu_nonmem_operand" "")
|
||||
(match_operand:V8HI 1 "spu_reg_operand" "")))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "spu_sf"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
|
||||
(minus:V4SI (match_operand:V4SI 2 "spu_nonmem_operand" "")
|
||||
(match_operand:V4SI 1 "spu_reg_operand" "")))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "spu_sfx"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
|
||||
(unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
|
||||
(match_operand:V4SI 1 "spu_reg_operand" "")
|
||||
(match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_SFX))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "spu_bg"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
|
||||
(unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
|
||||
(match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_BG))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "spu_bgx"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
|
||||
(unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
|
||||
(match_operand:V4SI 1 "spu_reg_operand" "")
|
||||
(match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_BGX))]
|
||||
""
|
||||
"")
|
||||
|
||||
;; integer multiply
|
||||
(define_insn "spu_mpy"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r,r")
|
||||
(mult:V4SI
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "spu_reg_operand" "r,r")
|
||||
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 2 "spu_arith_operand" "r,B")
|
||||
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))))]
|
||||
""
|
||||
"@
|
||||
mpy\t%0,%1,%2
|
||||
mpyi\t%0,%1,%H2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_insn "spu_mpyu"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r,r")
|
||||
(mult:V4SI
|
||||
(zero_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "spu_reg_operand" "r,r")
|
||||
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
|
||||
(zero_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 2 "spu_arith_operand" "r,B")
|
||||
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))))]
|
||||
""
|
||||
"@
|
||||
mpyu\t%0,%1,%2
|
||||
mpyui\t%0,%1,%H2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_insn "spu_mpya"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(plus:V4SI
|
||||
(mult:V4SI
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 2 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
|
||||
(match_operand:V4SI 3 "spu_reg_operand" "r")))]
|
||||
""
|
||||
"mpya\t%0,%1,%2,%3"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_insn "spu_mpyh"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(ashift:V4SI
|
||||
(mult:V4SI
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 2 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
|
||||
(const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))]
|
||||
""
|
||||
"mpyh\t%0,%1,%2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_insn "spu_mpys"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(ashiftrt:V4SI
|
||||
(mult:V4SI
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 2 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
|
||||
(const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))]
|
||||
""
|
||||
"mpys\t%0,%1,%2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_insn "spu_mpyhhu"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(mult:V4SI
|
||||
(zero_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
|
||||
(zero_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 2 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))))]
|
||||
""
|
||||
"mpyhhu\t%0,%1,%2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_insn "spu_mpyhh"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(mult:V4SI
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 2 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))))]
|
||||
""
|
||||
"mpyhh\t%0,%1,%2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_insn "spu_mpyhhau"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(plus:V4SI
|
||||
(mult:V4SI
|
||||
(zero_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
|
||||
(zero_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 2 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))
|
||||
(match_operand:V4SI 3 "spu_reg_operand" "0")))]
|
||||
""
|
||||
"mpyhhau\t%0,%1,%2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_insn "spu_mpyhha"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(plus:V4SI
|
||||
(mult:V4SI
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 2 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))
|
||||
(match_operand:V4SI 3 "spu_reg_operand" "0")))]
|
||||
""
|
||||
"mpyhha\t%0,%1,%2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
;; form select mask
|
||||
(define_insn "spu_fsmb"
|
||||
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r,r")
|
||||
(unspec:V16QI [(match_operand:SI 1 "spu_nonmem_operand" "r,MN")] UNSPEC_FSMB))]
|
||||
""
|
||||
"@
|
||||
fsmb\t%0,%1
|
||||
fsmbi\t%0,%1"
|
||||
[(set_attr "type" "shuf")])
|
||||
|
||||
(define_insn "spu_fsmh"
|
||||
[(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
|
||||
(unspec:V8HI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSMH))]
|
||||
""
|
||||
"fsmh\t%0,%1"
|
||||
[(set_attr "type" "shuf")])
|
||||
|
||||
(define_insn "spu_fsm"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(unspec:V4SI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSM))]
|
||||
""
|
||||
"fsm\t%0,%1"
|
||||
[(set_attr "type" "shuf")])
|
||||
|
||||
|
||||
;; gather bits
|
||||
(define_insn "spu_gbb"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(unspec:V4SI [(match_operand:V16QI 1 "spu_reg_operand" "r")] UNSPEC_GBB))]
|
||||
""
|
||||
"gbb\t%0,%1"
|
||||
[(set_attr "type" "shuf")])
|
||||
|
||||
(define_insn "spu_gbh"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(unspec:V4SI [(match_operand:V8HI 1 "spu_reg_operand" "r")] UNSPEC_GBH))]
|
||||
""
|
||||
"gbh\t%0,%1"
|
||||
[(set_attr "type" "shuf")])
|
||||
|
||||
(define_insn "spu_gb"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_GB))]
|
||||
""
|
||||
"gb\t%0,%1"
|
||||
[(set_attr "type" "shuf")])
|
||||
|
||||
;; misc byte operations
|
||||
(define_insn "spu_avgb"
|
||||
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
|
||||
(unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r")
|
||||
(match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_AVGB))]
|
||||
""
|
||||
"avgb\t%0,%1,%2"
|
||||
[(set_attr "type" "fxb")])
|
||||
|
||||
(define_insn "spu_absdb"
|
||||
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
|
||||
(unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r")
|
||||
(match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_ABSDB))]
|
||||
""
|
||||
"absdb\t%0,%1,%2"
|
||||
[(set_attr "type" "fxb")])
|
||||
|
||||
(define_insn "spu_sumb"
|
||||
[(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
|
||||
(unspec:V8HI [(match_operand:V16QI 1 "spu_reg_operand" "r")
|
||||
(match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_SUMB))]
|
||||
""
|
||||
"sumb\t%0,%1,%2"
|
||||
[(set_attr "type" "fxb")])
|
||||
|
||||
;; sign extend
|
||||
(define_insn "spu_xsbh"
|
||||
[(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
|
||||
(sign_extend:V8HI
|
||||
(vec_select:V8QI
|
||||
(match_operand:V16QI 1 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)
|
||||
(const_int 9)(const_int 11)(const_int 13)(const_int 15)]))))]
|
||||
""
|
||||
"xsbh\t%0,%1")
|
||||
|
||||
(define_insn "spu_xshw"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(sign_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))]
|
||||
""
|
||||
"xshw\t%0,%1")
|
||||
|
||||
(define_insn "spu_xswd"
|
||||
[(set (match_operand:V2DI 0 "spu_reg_operand" "=r")
|
||||
(sign_extend:V2DI
|
||||
(vec_select:V2SI
|
||||
(match_operand:V4SI 1 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 1)(const_int 3)]))))]
|
||||
""
|
||||
"xswd\t%0,%1")
|
||||
|
||||
;; or across
|
||||
|
||||
(define_insn "spu_orx"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_ORX))]
|
||||
""
|
||||
"orx\t%0,%1")
|
||||
|
||||
|
||||
;; compare & halt
|
||||
(define_insn "spu_heq"
|
||||
[(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
|
||||
(match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HEQ)]
|
||||
""
|
||||
"@
|
||||
heq\t%0,%1
|
||||
heqi\t%0,%1")
|
||||
|
||||
(define_insn "spu_hgt"
|
||||
[(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
|
||||
(match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HGT)]
|
||||
""
|
||||
"@
|
||||
hgt\t%0,%1
|
||||
hgti\t%0,%1")
|
||||
|
||||
(define_insn "spu_hlgt"
|
||||
[(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
|
||||
(match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HLGT)]
|
||||
""
|
||||
"@
|
||||
hlgt\t%0,%1
|
||||
hlgti\t%0,%1")
|
||||
|
||||
;; branches
|
||||
|
||||
;; The description below hides the fact that bisled conditionally
|
||||
;; executes the call depending on the value in channel 0. This was
|
||||
;; done so that the description would conform to the format of a call
|
||||
;; insn. Otherwise (if this were not part of call insn), the link
|
||||
;; register, $lr, would not be saved/restored in the prologue/epilogue.
|
||||
|
||||
(define_insn "spu_bisled"
|
||||
[(parallel
|
||||
[(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
|
||||
(const_int 0))
|
||||
(clobber (reg:SI 0))
|
||||
(clobber (reg:SI 130))
|
||||
(use (match_operand:SI 1 "address_operand" ""))
|
||||
(use (const_int 0))])]
|
||||
""
|
||||
"bisled\t$lr,%0"
|
||||
[(set_attr "type" "br")])
|
||||
|
||||
(define_insn "spu_bisledd"
|
||||
[(parallel
|
||||
[(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
|
||||
(const_int 0))
|
||||
(clobber (reg:SI 0))
|
||||
(clobber (reg:SI 130))
|
||||
(use (match_operand:SI 1 "address_operand" ""))
|
||||
(use (const_int 1))])]
|
||||
""
|
||||
"bisledd\t$lr,%0"
|
||||
[(set_attr "type" "br")])
|
||||
|
||||
(define_insn "spu_bislede"
|
||||
[(parallel
|
||||
[(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
|
||||
(const_int 0))
|
||||
(clobber (reg:SI 0))
|
||||
(clobber (reg:SI 130))
|
||||
(use (match_operand:SI 1 "address_operand" ""))
|
||||
(use (const_int 2))])]
|
||||
""
|
||||
"bislede\t$lr,%0"
|
||||
[(set_attr "type" "br")])
|
||||
|
||||
;; float convert
|
||||
(define_insn "spu_csflt"
|
||||
[(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
|
||||
(unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand" "r")
|
||||
(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_CSFLT ))]
|
||||
""
|
||||
"csflt\t%0,%1,%2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_insn "spu_cflts"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand" "r")
|
||||
(match_operand:SI 2 "immediate_operand" "J")] UNSPEC_CFLTS ))]
|
||||
""
|
||||
"cflts\t%0,%1,%2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_insn "spu_cuflt"
|
||||
[(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
|
||||
(unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand" "r")
|
||||
(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_CUFLT ))]
|
||||
""
|
||||
"cuflt\t%0,%1,%2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_insn "spu_cfltu"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand" "r")
|
||||
(match_operand:SI 2 "immediate_operand" "J")] UNSPEC_CFLTU ))]
|
||||
""
|
||||
"cfltu\t%0,%1,%2"
|
||||
[(set_attr "type" "fp7")])
|
||||
|
||||
(define_expand "spu_frds"
|
||||
[(set (match_operand:V4SF 0 "spu_reg_operand" "")
|
||||
(vec_select:V4SF
|
||||
(vec_concat:V4SF
|
||||
(float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" ""))
|
||||
(match_dup:V2SF 2))
|
||||
(parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
|
||||
""
|
||||
"operands[2] = spu_const(V2SFmode, 0);")
|
||||
|
||||
(define_insn "_frds"
|
||||
[(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
|
||||
(vec_select:V4SF
|
||||
(vec_concat:V4SF
|
||||
(float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" "r"))
|
||||
(match_operand:V2SF 2 "vec_imm_operand" "i"))
|
||||
(parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
|
||||
""
|
||||
"frds\t%0,%1"
|
||||
[(set_attr "type" "fpd")])
|
||||
|
||||
(define_insn "spu_fesd"
|
||||
[(set (match_operand:V2DF 0 "spu_reg_operand" "=r")
|
||||
(float_extend:V2DF
|
||||
(vec_select:V2SF
|
||||
(match_operand:V4SF 1 "spu_reg_operand" "r")
|
||||
(parallel [(const_int 0)(const_int 2)]))))]
|
||||
""
|
||||
"fesd\t%0,%1"
|
||||
[(set_attr "type" "fpd")])
|
||||
|
||||
;; control
|
||||
(define_insn "spu_stop"
|
||||
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "M")] UNSPEC_STOP)]
|
||||
""
|
||||
"stop\t%0"
|
||||
[(set_attr "type" "br")])
|
||||
|
||||
(define_insn "spu_stopd"
|
||||
[(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r")
|
||||
(match_operand:SI 1 "spu_reg_operand" "r")
|
||||
(match_operand:SI 2 "spu_reg_operand" "r")] UNSPEC_STOPD)]
|
||||
""
|
||||
"stopd\t%0,%1,%2"
|
||||
[(set_attr "type" "br")])
|
||||
|
||||
;; interrupt disable/enable
|
||||
;; Register 131 is used exclusively for enabling/disabling interrupts.
|
||||
;; It is marked as a global reg and the instructions clobber mem, so it will
|
||||
;; not be incorrectly optimized.
|
||||
(define_expand "spu_idisable"
|
||||
[(parallel
|
||||
[(set (reg:INTR 131) (const_int 0))
|
||||
(clobber (match_dup:SI 0))
|
||||
(clobber (mem:BLK (scratch)))])]
|
||||
""
|
||||
"operands[0] = gen_reg_rtx (SImode);")
|
||||
|
||||
(define_expand "spu_ienable"
|
||||
[(parallel
|
||||
[(set (reg:INTR 131) (const_int 1))
|
||||
(clobber (match_dup:SI 0))
|
||||
(clobber (mem:BLK (scratch)))])]
|
||||
""
|
||||
"operands[0] = gen_reg_rtx (SImode);")
|
||||
|
||||
(define_insn "set_intr"
|
||||
[(set (reg:INTR 131) (match_operand 1 "const_int_operand" "i"))
|
||||
(clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
|
||||
(clobber (mem:BLK (scratch)))]
|
||||
"! flag_pic"
|
||||
"ila\t%0,.+8\;bi%I1\t%0"
|
||||
[(set_attr "length" "8")
|
||||
(set_attr "type" "multi0")])
|
||||
|
||||
(define_insn "set_intr_pic"
|
||||
[(set (reg:INTR 131) (match_operand 1 "const_int_operand" "i"))
|
||||
(clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
|
||||
(clobber (mem:BLK (scratch)))]
|
||||
"flag_pic"
|
||||
"brsl\t%0,.+4\;ai\t%0,%0,8\;bi%I1\t%0"
|
||||
[(set_attr "length" "12")
|
||||
(set_attr "type" "multi1")])
|
||||
|
||||
(define_expand "movintrcc"
|
||||
[(parallel
|
||||
[(set (match_operand:INTR 0 "spu_reg_operand" "")
|
||||
(if_then_else:INTR (match_operand 1 "branch_comparison_operator" "")
|
||||
(match_operand 3 "const_int_operand" "")
|
||||
(match_operand:INTR 2 "spu_reg_operand" "")))
|
||||
(clobber (match_dup:SI 4))
|
||||
(clobber (mem:BLK (scratch)))])]
|
||||
""
|
||||
{ /* We've swapped operands 2 and 3 in the pattern, reverse the
|
||||
condition code too. */
|
||||
PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1])));
|
||||
operands[4] = gen_reg_rtx (SImode);
|
||||
})
|
||||
|
||||
(define_insn "set_intr_cc"
|
||||
[(set (reg:INTR 131)
|
||||
(if_then_else:INTR
|
||||
(match_operator 1 "branch_comparison_operator"
|
||||
[(match_operand 2 "spu_reg_operand" "r")
|
||||
(const_int 0)])
|
||||
(match_operand:SI 3 "const_int_operand" "i")
|
||||
(reg:INTR 131)))
|
||||
(clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
|
||||
(clobber (mem:BLK (scratch)))]
|
||||
"! flag_pic"
|
||||
"ila\t%0,.+8\;bi%b2%b1z%I3\t%2,%0"
|
||||
[(set_attr "length" "8")
|
||||
(set_attr "type" "multi0")])
|
||||
|
||||
(define_insn "set_intr_cc_pic"
|
||||
[(set (reg:INTR 131)
|
||||
(if_then_else:INTR
|
||||
(match_operator 1 "branch_comparison_operator"
|
||||
[(match_operand 2 "spu_reg_operand" "r")
|
||||
(const_int 0)])
|
||||
(match_operand:SI 3 "const_int_operand" "i")
|
||||
(reg:INTR 131)))
|
||||
(clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
|
||||
(clobber (mem:BLK (scratch)))]
|
||||
"flag_pic"
|
||||
"brsl\t%0,.+4\;ai\t%0,%0,8\;%b2%b1z%I3\t%2,%0"
|
||||
[(set_attr "length" "12")
|
||||
(set_attr "type" "multi1")])
|
||||
|
||||
(define_insn "set_intr_return"
|
||||
[(set (reg:INTR 131) (match_operand 0 "const_int_operand" "i"))
|
||||
(return)]
|
||||
""
|
||||
"bi%I0\t$lr"
|
||||
[(set_attr "type" "br")])
|
||||
|
||||
(define_peephole2
|
||||
[(parallel
|
||||
[(set (reg:INTR 131) (match_operand 0 "const_int_operand"))
|
||||
(clobber (match_operand:SI 1 "spu_reg_operand"))
|
||||
(clobber (mem:BLK (scratch)))])
|
||||
(use (reg:SI 0))
|
||||
(return)]
|
||||
""
|
||||
[(use (reg:SI 0))
|
||||
(parallel
|
||||
[(set (reg:INTR 131) (match_dup 0))
|
||||
(return)])]
|
||||
"")
|
||||
|
||||
;; special purpose registers
|
||||
(define_insn "spu_fscrrd"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(unspec_volatile:V4SI [(const_int 6)] UNSPEC_FSCRRD))]
|
||||
""
|
||||
"fscrrd\t%0"
|
||||
[(set_attr "type" "spr")])
|
||||
|
||||
(define_insn "spu_fscrwr"
|
||||
[(unspec_volatile [(match_operand:V4SI 0 "spu_reg_operand" "r")] UNSPEC_FSCRWR)]
|
||||
""
|
||||
"fscrwr\t$0,%0"
|
||||
[(set_attr "type" "spr")])
|
||||
|
||||
(define_insn "spu_mfspr"
|
||||
[(set (match_operand:SI 0 "spu_reg_operand" "=r")
|
||||
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_MFSPR))]
|
||||
""
|
||||
"mfspr\t%0,$sp%1"
|
||||
[(set_attr "type" "spr")])
|
||||
|
||||
(define_insn "spu_mtspr"
|
||||
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
|
||||
(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_MTSPR)]
|
||||
""
|
||||
"mtspr\t$sp%0,%1"
|
||||
[(set_attr "type" "spr")])
|
||||
|
||||
;; channels
|
||||
(define_expand "spu_rdch"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
|
||||
(unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RDCH))]
|
||||
""
|
||||
"{
|
||||
if (spu_safe_dma (INTVAL (operands[1])))
|
||||
{
|
||||
emit_insn (gen_spu_rdch_clobber (operands[0], operands[1]));
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
(define_expand "spu_rchcnt"
|
||||
[(set (match_operand:SI 0 "spu_reg_operand" "")
|
||||
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RCHCNT))]
|
||||
""
|
||||
"{
|
||||
if (spu_safe_dma (INTVAL (operands[1])))
|
||||
{
|
||||
emit_insn (gen_spu_rchcnt_clobber (operands[0], operands[1]));
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
(define_expand "spu_wrch"
|
||||
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "")
|
||||
(match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_WRCH)]
|
||||
""
|
||||
"{
|
||||
if (spu_safe_dma (INTVAL (operands[0])))
|
||||
{
|
||||
emit_insn (gen_spu_wrch_clobber (operands[0], operands[1]));
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
(define_insn "spu_rdch_noclobber"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH))]
|
||||
""
|
||||
"rdch\t%0,$ch%1"
|
||||
[(set_attr "type" "spr")])
|
||||
|
||||
(define_insn "spu_rchcnt_noclobber"
|
||||
[(set (match_operand:SI 0 "spu_reg_operand" "=r")
|
||||
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT))]
|
||||
""
|
||||
"rchcnt\t%0,$ch%1"
|
||||
[(set_attr "type" "spr")])
|
||||
|
||||
(define_insn "spu_wrch_noclobber"
|
||||
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
|
||||
(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH)]
|
||||
""
|
||||
"wrch\t$ch%0,%1"
|
||||
[(set_attr "type" "spr")])
|
||||
|
||||
(define_insn "spu_rdch_clobber"
|
||||
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
|
||||
(unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH))
|
||||
(clobber (mem:BLK (scratch)))]
|
||||
""
|
||||
"rdch\t%0,$ch%1"
|
||||
[(set_attr "type" "spr")])
|
||||
|
||||
(define_insn "spu_rchcnt_clobber"
|
||||
[(set (match_operand:SI 0 "spu_reg_operand" "=r")
|
||||
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT))
|
||||
(clobber (mem:BLK (scratch)))]
|
||||
""
|
||||
"rchcnt\t%0,$ch%1"
|
||||
[(set_attr "type" "spr")])
|
||||
|
||||
(define_insn "spu_wrch_clobber"
|
||||
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
|
||||
(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH)
|
||||
(clobber (mem:BLK (scratch)))]
|
||||
""
|
||||
"wrch\t$ch%0,%1"
|
||||
[(set_attr "type" "spr")])
|
||||
|
||||
(define_expand "spu_splats"
|
||||
[(set (match_operand 0 "spu_reg_operand" "")
|
||||
(vec_duplicate (match_operand 1 "spu_nonmem_operand" "")))]
|
||||
""
|
||||
{
|
||||
spu_builtin_splats(operands);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "spu_extract"
|
||||
[(set (match_operand 0 "spu_reg_operand" "")
|
||||
(unspec [(match_operand 1 "spu_reg_operand" "")
|
||||
(match_operand 2 "spu_nonmem_operand" "")] 0))]
|
||||
""
|
||||
{
|
||||
spu_builtin_extract (operands);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "spu_insert"
|
||||
[(set (match_operand 0 "spu_reg_operand" "")
|
||||
(unspec [(match_operand 1 "spu_reg_operand" "")
|
||||
(match_operand 2 "spu_reg_operand" "")
|
||||
(match_operand:SI 3 "spu_nonmem_operand" "")] 0))]
|
||||
""
|
||||
{
|
||||
spu_builtin_insert(operands);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "spu_promote"
|
||||
[(set (match_operand 0 "spu_reg_operand" "")
|
||||
(unspec [(match_operand 1 "spu_reg_operand" "")
|
||||
(match_operand:SI 2 "immediate_operand" "")] 0))]
|
||||
""
|
||||
{
|
||||
spu_builtin_promote(operands);
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Currently doing nothing with this but expanding its args.
|
||||
(define_expand "spu_align_hint"
|
||||
[(unspec [(match_operand:SI 0 "address_operand" "")
|
||||
(match_operand:SI 1 "immediate_operand" "")
|
||||
(match_operand:SI 2 "immediate_operand" "")] 0)]
|
||||
""
|
||||
{
|
||||
DONE;
|
||||
})
|
||||
|
||||
443
gcc/config/spu/spu-c.c
Normal file
443
gcc/config/spu/spu-c.c
Normal file
|
|
@ -0,0 +1,443 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#include "config.h"
|
||||
#include "system.h"
|
||||
#include "coretypes.h"
|
||||
#include "tm.h"
|
||||
#include "cpplib.h"
|
||||
#include "tree.h"
|
||||
#include "c-tree.h"
|
||||
#include "c-pragma.h"
|
||||
#include "function.h"
|
||||
#include "rtl.h"
|
||||
#include "expr.h"
|
||||
#include "errors.h"
|
||||
#include "tm_p.h"
|
||||
#include "langhooks.h"
|
||||
#include "insn-config.h"
|
||||
#include "insn-codes.h"
|
||||
#include "recog.h"
|
||||
#include "optabs.h"
|
||||
#include "spu-builtins.h"
|
||||
|
||||
static rtx spu_expand_builtin_1 (struct spu_builtin_description *d,
|
||||
tree arglist, rtx target);
|
||||
static void spu_check_builtin_parm (struct spu_builtin_description *, rtx,
|
||||
int);
|
||||
static void expand_builtin_args (struct spu_builtin_description *, tree, rtx,
|
||||
rtx[]);
|
||||
static rtx spu_force_reg (enum machine_mode mode, rtx op);
|
||||
|
||||
/* Builtin types, data and prototypes. */
|
||||
struct spu_builtin_range
|
||||
{
|
||||
int low, high;
|
||||
};
|
||||
|
||||
static struct spu_builtin_range spu_builtin_range[] = {
|
||||
{-0x40ll, 0x7fll}, /* SPU_BTI_7 */
|
||||
{-0x40ll, 0x3fll}, /* SPU_BTI_S7 */
|
||||
{0ll, 0x7fll}, /* SPU_BTI_U7 */
|
||||
{-0x200ll, 0x1ffll}, /* SPU_BTI_S10 */
|
||||
{-0x2000ll, 0x1fffll}, /* SPU_BTI_S10_4 */
|
||||
{0ll, 0x3fffll}, /* SPU_BTI_U14 */
|
||||
{-0x8000ll, 0xffffll}, /* SPU_BTI_16 */
|
||||
{-0x8000ll, 0x7fffll}, /* SPU_BTI_S16 */
|
||||
{-0x20000ll, 0x1ffffll}, /* SPU_BTI_S16_2 */
|
||||
{0ll, 0xffffll}, /* SPU_BTI_U16 */
|
||||
{0ll, 0x3ffffll}, /* SPU_BTI_U16_2 */
|
||||
{0ll, 0x3ffffll}, /* SPU_BTI_U18 */
|
||||
};
|
||||
|
||||
|
||||
/* Helper for spu_resolve_overloaded_builtin. */
|
||||
static tree
|
||||
spu_build_overload_builtin (tree fndecl, tree fnargs)
|
||||
{
|
||||
tree param, param_type;
|
||||
tree ret_type = TREE_TYPE (TREE_TYPE (fndecl));
|
||||
tree arg, arglist = NULL_TREE;
|
||||
tree val;
|
||||
|
||||
for (param = TYPE_ARG_TYPES (TREE_TYPE (fndecl)), arg = fnargs;
|
||||
param != void_list_node;
|
||||
param = TREE_CHAIN (param), arg = TREE_CHAIN (arg))
|
||||
{
|
||||
gcc_assert (arg != NULL_TREE);
|
||||
param_type = TREE_VALUE (param);
|
||||
val = default_conversion (TREE_VALUE (arg));
|
||||
val = fold_convert (param_type, val);
|
||||
|
||||
arglist = tree_cons (NULL_TREE, val, arglist);
|
||||
}
|
||||
gcc_assert (arg == NULL_TREE);
|
||||
arglist = nreverse (arglist);
|
||||
|
||||
return fold_convert (ret_type, build_function_call_expr (fndecl, arglist));
|
||||
}
|
||||
|
||||
/* target hook for resolve_overloaded_builtin(). Returns a function call
|
||||
RTX if we can resolve the overloaded builtin */
|
||||
tree
|
||||
spu_resolve_overloaded_builtin (tree fndecl, tree fnargs)
|
||||
{
|
||||
spu_function_code new_fcode, fcode =
|
||||
DECL_FUNCTION_CODE (fndecl) - END_BUILTINS;
|
||||
struct spu_builtin_description *desc;
|
||||
tree match = NULL_TREE;
|
||||
|
||||
/* The vector types are not available if the backend is not initalized */
|
||||
gcc_assert (!flag_preprocess_only);
|
||||
|
||||
desc = &spu_builtins[fcode];
|
||||
if (desc->type != B_OVERLOAD)
|
||||
return NULL_TREE;
|
||||
|
||||
/* Compare the signature of each internal builtin function with the
|
||||
function arguments until a match is found. */
|
||||
|
||||
for (new_fcode = fcode + 1; spu_builtins[new_fcode].type == B_INTERNAL;
|
||||
new_fcode++)
|
||||
{
|
||||
tree decl = spu_builtins[new_fcode].fndecl;
|
||||
tree params = TYPE_ARG_TYPES (TREE_TYPE (decl));
|
||||
tree arg, param;
|
||||
int p;
|
||||
|
||||
for (param = params, arg = fnargs, p = 0;
|
||||
param != void_list_node;
|
||||
param = TREE_CHAIN (param), arg = TREE_CHAIN (arg), p++)
|
||||
{
|
||||
tree var, arg_type, param_type = TREE_VALUE (param);
|
||||
|
||||
if (!arg)
|
||||
{
|
||||
error ("insufficient arguments to overloaded function %s",
|
||||
desc->name);
|
||||
return error_mark_node;
|
||||
}
|
||||
|
||||
var = TREE_VALUE (arg);
|
||||
|
||||
if (TREE_CODE (var) == NON_LVALUE_EXPR)
|
||||
var = TREE_OPERAND (var, 0);
|
||||
|
||||
if (TREE_CODE (var) == ERROR_MARK)
|
||||
return NULL_TREE; /* Let somebody else deal with the problem. */
|
||||
|
||||
arg_type = TREE_TYPE (var);
|
||||
|
||||
/* The intrinsics spec does not specify precisely how to
|
||||
resolve generic intrinsics. We require an exact match
|
||||
for vector types and let C do it's usual parameter type
|
||||
checking/promotions for scalar arguments, except for the
|
||||
first argument of intrinsics which don't have a vector
|
||||
parameter. */
|
||||
if ((TREE_CODE (param_type) == VECTOR_TYPE
|
||||
|| ((fcode == SPU_SPLATS || fcode == SPU_PROMOTE
|
||||
|| fcode == SPU_HCMPEQ || fcode == SPU_HCMPGT
|
||||
|| fcode == SPU_MASKB || fcode == SPU_MASKH
|
||||
|| fcode == SPU_MASKW) && p == 0))
|
||||
&& !comptypes (TYPE_MAIN_VARIANT (param_type),
|
||||
TYPE_MAIN_VARIANT (arg_type)))
|
||||
break;
|
||||
}
|
||||
if (param == void_list_node)
|
||||
{
|
||||
if (arg)
|
||||
{
|
||||
error ("too many arguments to overloaded function %s",
|
||||
desc->name);
|
||||
return error_mark_node;
|
||||
}
|
||||
|
||||
match = decl;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (match == NULL_TREE)
|
||||
{
|
||||
error ("parameter list does not match a valid signature for %s()",
|
||||
desc->name);
|
||||
return error_mark_node;
|
||||
}
|
||||
|
||||
return spu_build_overload_builtin (match, fnargs);
|
||||
}
|
||||
|
||||
static void
|
||||
spu_check_builtin_parm (struct spu_builtin_description *d, rtx op, int p)
|
||||
{
|
||||
HOST_WIDE_INT v = 0;
|
||||
int lsbits;
|
||||
/* Check the range of immediate operands. */
|
||||
if (p >= SPU_BTI_7 && p <= SPU_BTI_U18)
|
||||
{
|
||||
int range = p - SPU_BTI_7;
|
||||
if (!CONSTANT_P (op)
|
||||
|| (GET_CODE (op) == CONST_INT
|
||||
&& (INTVAL (op) < spu_builtin_range[range].low
|
||||
|| INTVAL (op) > spu_builtin_range[range].high)))
|
||||
error ("%s expects an integer literal in the range [%d, %d].",
|
||||
d->name,
|
||||
spu_builtin_range[range].low, spu_builtin_range[range].high);
|
||||
|
||||
if (GET_CODE (op) == CONST
|
||||
&& (GET_CODE (XEXP (op, 0)) == PLUS
|
||||
|| GET_CODE (XEXP (op, 0)) == MINUS))
|
||||
{
|
||||
v = INTVAL (XEXP (XEXP (op, 0), 1));
|
||||
op = XEXP (XEXP (op, 0), 0);
|
||||
}
|
||||
else if (GET_CODE (op) == CONST_INT)
|
||||
v = INTVAL (op);
|
||||
|
||||
switch (p)
|
||||
{
|
||||
case SPU_BTI_S10_4:
|
||||
lsbits = 4;
|
||||
break;
|
||||
case SPU_BTI_U16_2:
|
||||
/* This is only used in lqa, and stqa. Even though the insns
|
||||
encode 16 bits of the address (all but the 2 least
|
||||
significant), only 14 bits are used because it is masked to
|
||||
be 16 byte aligned. */
|
||||
lsbits = 4;
|
||||
break;
|
||||
case SPU_BTI_S16_2:
|
||||
/* This is used for lqr and stqr. */
|
||||
lsbits = 2;
|
||||
break;
|
||||
default:
|
||||
lsbits = 0;
|
||||
}
|
||||
|
||||
if (GET_CODE (op) == LABEL_REF
|
||||
|| (GET_CODE (op) == SYMBOL_REF
|
||||
&& SYMBOL_REF_FUNCTION_P (op))
|
||||
|| (INTVAL (op) & ((1 << lsbits) - 1)) != 0)
|
||||
warning (0, "%d least significant bits of %s are ignored.", lsbits,
|
||||
d->name);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
expand_builtin_args (struct spu_builtin_description *d, tree arglist,
|
||||
rtx target, rtx ops[])
|
||||
{
|
||||
enum insn_code icode = d->icode;
|
||||
int i = 0;
|
||||
|
||||
/* Expand the arguments into rtl. */
|
||||
|
||||
if (d->parm[0] != SPU_BTI_VOID)
|
||||
ops[i++] = target;
|
||||
|
||||
for (; i < insn_data[icode].n_operands; i++)
|
||||
{
|
||||
tree arg = TREE_VALUE (arglist);
|
||||
if (arg == 0)
|
||||
abort ();
|
||||
ops[i] = expand_expr (arg, NULL_RTX, VOIDmode, 0);
|
||||
arglist = TREE_CHAIN (arglist);
|
||||
}
|
||||
}
|
||||
|
||||
static rtx
|
||||
spu_expand_builtin_1 (struct spu_builtin_description *d,
|
||||
tree arglist, rtx target)
|
||||
{
|
||||
rtx pat;
|
||||
rtx ops[8];
|
||||
enum insn_code icode = d->icode;
|
||||
enum machine_mode mode, tmode;
|
||||
int i, p;
|
||||
tree return_type;
|
||||
|
||||
/* Set up ops[] with values from arglist. */
|
||||
expand_builtin_args (d, arglist, target, ops);
|
||||
|
||||
/* Handle the target operand which must be operand 0. */
|
||||
i = 0;
|
||||
if (d->parm[0] != SPU_BTI_VOID)
|
||||
{
|
||||
|
||||
/* We prefer the mode specified for the match_operand otherwise
|
||||
use the mode from the builtin function prototype. */
|
||||
tmode = insn_data[d->icode].operand[0].mode;
|
||||
if (tmode == VOIDmode)
|
||||
tmode = TYPE_MODE (spu_builtin_types[d->parm[0]]);
|
||||
|
||||
/* Try to use target because not using it can lead to extra copies
|
||||
and when we are using all of the registers extra copies leads
|
||||
to extra spills. */
|
||||
if (target && GET_CODE (target) == REG && GET_MODE (target) == tmode)
|
||||
ops[0] = target;
|
||||
else
|
||||
target = ops[0] = gen_reg_rtx (tmode);
|
||||
|
||||
if (!(*insn_data[icode].operand[0].predicate) (ops[0], tmode))
|
||||
abort ();
|
||||
|
||||
i++;
|
||||
}
|
||||
|
||||
/* Ignore align_hint, but still expand it's args in case they have
|
||||
side effects. */
|
||||
if (icode == CODE_FOR_spu_align_hint)
|
||||
return 0;
|
||||
|
||||
/* Handle the rest of the operands. */
|
||||
for (p = 1; i < insn_data[icode].n_operands; i++, p++)
|
||||
{
|
||||
if (insn_data[d->icode].operand[i].mode != VOIDmode)
|
||||
mode = insn_data[d->icode].operand[i].mode;
|
||||
else
|
||||
mode = TYPE_MODE (spu_builtin_types[d->parm[i]]);
|
||||
|
||||
/* mode can be VOIDmode here for labels */
|
||||
|
||||
/* For specific intrinsics with an immediate operand, e.g.,
|
||||
si_ai(), we sometimes need to convert the scalar argument to a
|
||||
vector argument by splatting the scalar. */
|
||||
if (VECTOR_MODE_P (mode)
|
||||
&& (GET_CODE (ops[i]) == CONST_INT
|
||||
|| GET_MODE_CLASS (GET_MODE (ops[i])) == MODE_INT
|
||||
|| GET_MODE_CLASS (GET_MODE (ops[i])) == MODE_FLOAT))
|
||||
{
|
||||
if (GET_CODE (ops[i]) == CONST_INT)
|
||||
ops[i] = spu_const (mode, INTVAL (ops[i]));
|
||||
else
|
||||
{
|
||||
rtx reg = gen_reg_rtx (mode);
|
||||
enum machine_mode imode = GET_MODE_INNER (mode);
|
||||
if (!spu_nonmem_operand (ops[i], GET_MODE (ops[i])))
|
||||
ops[i] = force_reg (GET_MODE (ops[i]), ops[i]);
|
||||
if (imode != GET_MODE (ops[i]))
|
||||
ops[i] = convert_to_mode (imode, ops[i],
|
||||
TYPE_UNSIGNED (spu_builtin_types
|
||||
[d->parm[i]]));
|
||||
emit_insn (gen_spu_splats (reg, ops[i]));
|
||||
ops[i] = reg;
|
||||
}
|
||||
}
|
||||
|
||||
if (!(*insn_data[icode].operand[i].predicate) (ops[i], mode))
|
||||
ops[i] = spu_force_reg (mode, ops[i]);
|
||||
|
||||
spu_check_builtin_parm (d, ops[i], d->parm[p]);
|
||||
}
|
||||
|
||||
switch (insn_data[icode].n_operands)
|
||||
{
|
||||
case 0:
|
||||
pat = GEN_FCN (icode) (0);
|
||||
break;
|
||||
case 1:
|
||||
pat = GEN_FCN (icode) (ops[0]);
|
||||
break;
|
||||
case 2:
|
||||
pat = GEN_FCN (icode) (ops[0], ops[1]);
|
||||
break;
|
||||
case 3:
|
||||
pat = GEN_FCN (icode) (ops[0], ops[1], ops[2]);
|
||||
break;
|
||||
case 4:
|
||||
pat = GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]);
|
||||
break;
|
||||
case 5:
|
||||
pat = GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3], ops[4]);
|
||||
break;
|
||||
case 6:
|
||||
pat = GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3], ops[4], ops[5]);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
||||
if (!pat)
|
||||
abort ();
|
||||
|
||||
if (d->type == B_CALL || d->type == B_BISLED)
|
||||
emit_call_insn (pat);
|
||||
else if (d->type == B_JUMP)
|
||||
{
|
||||
emit_jump_insn (pat);
|
||||
emit_barrier ();
|
||||
}
|
||||
else
|
||||
emit_insn (pat);
|
||||
|
||||
return_type = spu_builtin_types[d->parm[0]];
|
||||
if (d->parm[0] != SPU_BTI_VOID
|
||||
&& GET_MODE (target) != TYPE_MODE (return_type))
|
||||
{
|
||||
/* target is the return value. It should always be the mode of
|
||||
the builtin function prototype. */
|
||||
target = spu_force_reg (TYPE_MODE (return_type), target);
|
||||
}
|
||||
|
||||
return target;
|
||||
}
|
||||
|
||||
rtx
|
||||
spu_expand_builtin (tree exp,
|
||||
rtx target,
|
||||
rtx subtarget ATTRIBUTE_UNUSED,
|
||||
enum machine_mode mode ATTRIBUTE_UNUSED,
|
||||
int ignore ATTRIBUTE_UNUSED)
|
||||
{
|
||||
tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
|
||||
unsigned int fcode = DECL_FUNCTION_CODE (fndecl) - END_BUILTINS;
|
||||
tree arglist = TREE_OPERAND (exp, 1);
|
||||
struct spu_builtin_description *d;
|
||||
|
||||
if (fcode < NUM_SPU_BUILTINS)
|
||||
{
|
||||
d = &spu_builtins[fcode];
|
||||
|
||||
return spu_expand_builtin_1 (d, arglist, target);
|
||||
}
|
||||
abort ();
|
||||
}
|
||||
|
||||
static rtx
|
||||
spu_force_reg (enum machine_mode mode, rtx op)
|
||||
{
|
||||
rtx x, r;
|
||||
if (GET_MODE (op) == VOIDmode || GET_MODE (op) == BLKmode)
|
||||
{
|
||||
if ((SCALAR_INT_MODE_P (mode) && GET_CODE (op) == CONST_INT)
|
||||
|| GET_MODE (op) == BLKmode)
|
||||
return force_reg (mode, convert_to_mode (mode, op, 0));
|
||||
abort ();
|
||||
}
|
||||
|
||||
r = force_reg (GET_MODE (op), op);
|
||||
if (GET_MODE_SIZE (GET_MODE (op)) == GET_MODE_SIZE (mode))
|
||||
{
|
||||
x = simplify_gen_subreg (mode, r, GET_MODE (op), 0);
|
||||
if (x)
|
||||
return x;
|
||||
}
|
||||
|
||||
x = gen_reg_rtx (mode);
|
||||
emit_insn (gen_spu_convert (x, r));
|
||||
return x;
|
||||
}
|
||||
54
gcc/config/spu/spu-elf.h
Normal file
54
gcc/config/spu/spu-elf.h
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#ifndef OBJECT_FORMAT_ELF
|
||||
#error elf.h included before elfos.h
|
||||
#endif
|
||||
|
||||
#define BSS_SECTION_ASM_OP "\t.section .bss"
|
||||
|
||||
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
|
||||
asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
|
||||
|
||||
|
||||
#undef STARTFILE_SPEC
|
||||
#define STARTFILE_SPEC "crt1%O%s"
|
||||
|
||||
#undef ENDFILE_SPEC
|
||||
#define ENDFILE_SPEC "crtend1%O%s"
|
||||
|
||||
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
|
||||
|
||||
#define DWARF2_DEBUGGING_INFO 1
|
||||
#define DWARF2_ASM_LINE_DEBUG_INFO 1
|
||||
|
||||
#define SET_ASM_OP "\t.set\t"
|
||||
|
||||
#undef TARGET_ASM_NAMED_SECTION
|
||||
#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
|
||||
|
||||
#define EH_FRAME_IN_DATA_SECTION 1
|
||||
|
||||
#define LINK_SPEC "%{mlarge-mem: --defsym __stack=0xfffffff0 }"
|
||||
|
||||
#define LIB_SPEC \
|
||||
"-( %{!shared:%{g*:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}} -lgloss -)"
|
||||
|
||||
/* Turn off warnings in the assembler too. */
|
||||
#undef ASM_SPEC
|
||||
#define ASM_SPEC "%{w:-W}"
|
||||
|
||||
34
gcc/config/spu/spu-modes.def
Normal file
34
gcc/config/spu/spu-modes.def
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
/* Vector modes. */
|
||||
VECTOR_MODES (INT, 2); /* V2QI */
|
||||
VECTOR_MODES (INT, 4); /* V4QI V2HI */
|
||||
VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
|
||||
VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
|
||||
|
||||
|
||||
VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */
|
||||
VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
|
||||
|
||||
/* A special mode for the intr regsister so we can treat it differently
|
||||
for conditional moves. */
|
||||
RANDOM_MODE (INTR);
|
||||
|
||||
/* cse_insn needs an INT_MODE larger than WORD_MODE, otherwise some
|
||||
parts of it will go into an infinite loop. */
|
||||
INT_MODE (OI, 32);
|
||||
93
gcc/config/spu/spu-protos.h
Normal file
93
gcc/config/spu/spu-protos.h
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#ifndef _SPU_PROTOS_
|
||||
#define _SPU_PROTOS_
|
||||
|
||||
#include "rtl.h"
|
||||
|
||||
extern enum machine_mode spu_eh_return_filter_mode (void);
|
||||
extern void spu_cpu_cpp_builtins (struct cpp_reader * pfile);
|
||||
extern void builtin_define_std (const char *);
|
||||
extern void spu_override_options (void);
|
||||
extern int valid_subreg (rtx op);
|
||||
extern void spu_expand_extv (rtx * ops, int unsignedp);
|
||||
extern void spu_expand_insv (rtx * ops);
|
||||
extern int spu_expand_block_move (rtx * ops);
|
||||
extern void spu_emit_branch_or_set (int is_set, enum rtx_code code,
|
||||
rtx * operands);
|
||||
extern HOST_WIDE_INT const_double_to_hwint (rtx x);
|
||||
extern rtx hwint_to_const_double (enum machine_mode mode, HOST_WIDE_INT v);
|
||||
extern void print_operand_address (FILE * file, register rtx addr);
|
||||
extern void print_operand (FILE * file, rtx x, int code);
|
||||
extern int spu_saved_regs_size (void);
|
||||
extern int direct_return (void);
|
||||
extern void spu_expand_prologue (void);
|
||||
extern void spu_expand_epilogue (unsigned char sibcall_p);
|
||||
extern rtx spu_return_addr (int count, rtx frame);
|
||||
extern rtx spu_const (enum machine_mode mode, HOST_WIDE_INT val);
|
||||
extern struct rtx_def *spu_float_const (const char *string,
|
||||
enum machine_mode mode);
|
||||
extern int immediate_load_p (rtx op, enum machine_mode mode);
|
||||
extern int logical_immediate_p (rtx op, enum machine_mode mode);
|
||||
extern int iohl_immediate_p (rtx op, enum machine_mode mode);
|
||||
extern int arith_immediate_p (rtx op, enum machine_mode mode,
|
||||
HOST_WIDE_INT low, HOST_WIDE_INT high);
|
||||
extern int legitimate_const (rtx x, int aligned);
|
||||
extern int spu_constant_address_p (rtx x);
|
||||
extern int spu_legitimate_constant_p (rtx x);
|
||||
extern int spu_legitimate_address (enum machine_mode mode, rtx x,
|
||||
int reg_ok_strict);
|
||||
extern rtx spu_legitimize_address (rtx x, rtx oldx, enum machine_mode mode);
|
||||
extern int spu_initial_elimination_offset (int from, int to);
|
||||
extern rtx spu_function_value (tree type, tree func);
|
||||
extern rtx spu_function_arg (int cum, enum machine_mode mode, tree type,
|
||||
int named);
|
||||
extern void spu_va_start (tree valist, rtx nextarg);
|
||||
extern void spu_setup_incoming_varargs (int *cum, enum machine_mode mode,
|
||||
tree type, int *pretend_size,
|
||||
int no_rtl);
|
||||
extern void spu_conditional_register_usage (void);
|
||||
extern int aligned_mem_p (rtx mem);
|
||||
extern int spu_expand_mov (rtx * ops, enum machine_mode mode);
|
||||
extern void spu_split_load (rtx * ops);
|
||||
extern void spu_split_store (rtx * ops);
|
||||
extern int spu_valid_move (rtx * ops);
|
||||
extern int fsmbi_const_p (rtx x);
|
||||
extern void constant_to_array (enum machine_mode mode, rtx x,
|
||||
unsigned char *arr);
|
||||
extern rtx array_to_constant (enum machine_mode mode, unsigned char *arr);
|
||||
extern enum machine_mode spu_eh_return_filter_mode (void);
|
||||
extern void spu_allocate_stack (rtx op0, rtx op1);
|
||||
extern void spu_restore_stack_nonlocal (rtx op0, rtx op1);
|
||||
extern rtx spu_gen_subreg (enum machine_mode mode, rtx x);
|
||||
extern int spu_safe_dma(HOST_WIDE_INT channel);
|
||||
extern void spu_builtin_splats (rtx ops[]);
|
||||
extern void spu_builtin_extract (rtx ops[]);
|
||||
extern void spu_builtin_insert (rtx ops[]);
|
||||
extern void spu_builtin_promote (rtx ops[]);
|
||||
extern void spu_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt);
|
||||
extern void spu_expand_sign_extend (rtx ops[]);
|
||||
extern void spu_expand_vector_init (rtx target, rtx vals);
|
||||
|
||||
/* spu-c.c */
|
||||
extern tree spu_resolve_overloaded_builtin (tree fndecl, tree fnargs);
|
||||
extern rtx spu_expand_builtin (tree exp, rtx target, rtx subtarget,
|
||||
enum machine_mode mode, int ignore);
|
||||
extern rtx spu_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
|
||||
|
||||
#endif
|
||||
4469
gcc/config/spu/spu.c
Normal file
4469
gcc/config/spu/spu.c
Normal file
File diff suppressed because it is too large
Load diff
550
gcc/config/spu/spu.h
Normal file
550
gcc/config/spu/spu.h
Normal file
|
|
@ -0,0 +1,550 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
|
||||
/* Run-time Target */
|
||||
#define TARGET_CPU_CPP_BUILTINS() spu_cpu_cpp_builtins(pfile)
|
||||
|
||||
#define TARGET_VERSION fprintf (stderr, " (spu %s)", __DATE__);
|
||||
|
||||
#define OVERRIDE_OPTIONS spu_override_options()
|
||||
|
||||
extern int target_flags;
|
||||
|
||||
/* Default target_flags if no switches specified. */
|
||||
#ifndef TARGET_DEFAULT
|
||||
#define TARGET_DEFAULT (MASK_ERROR_RELOC | MASK_SAFE_DMA | MASK_BRANCH_HINTS)
|
||||
#endif
|
||||
|
||||
|
||||
/* Storage Layout */
|
||||
|
||||
#define BITS_BIG_ENDIAN 1
|
||||
|
||||
#define BYTES_BIG_ENDIAN 1
|
||||
|
||||
#define WORDS_BIG_ENDIAN 1
|
||||
|
||||
#define BITS_PER_UNIT 8
|
||||
|
||||
/* GCC uses word_mode in many places, assuming that it is the fastest
|
||||
integer mode. That is not the case for SPU though. We can't use
|
||||
32 here because (of some reason I can't remember.) */
|
||||
#define BITS_PER_WORD 128
|
||||
|
||||
#define UNITS_PER_WORD (BITS_PER_WORD/BITS_PER_UNIT)
|
||||
|
||||
/* We never actually change UNITS_PER_WORD, but defining this causes
|
||||
libgcc to use some different sizes of types when compiling. */
|
||||
#define MIN_UNITS_PER_WORD 4
|
||||
|
||||
#define POINTER_SIZE 32
|
||||
|
||||
#define PARM_BOUNDARY 128
|
||||
|
||||
#define STACK_BOUNDARY 128
|
||||
|
||||
/* We want it 8-byte aligned so we can properly use dual-issue
|
||||
instructions, which can only happen on an 8-byte aligned address. */
|
||||
#define FUNCTION_BOUNDARY 64
|
||||
|
||||
/* We would like to allow a larger alignment for data objects (for DMA)
|
||||
but the aligned attribute is limited by BIGGEST_ALIGNMENT. We don't
|
||||
define BIGGEST_ALIGNMENT as larger because it is used in other places
|
||||
and would end up wasting space. (Is this still true?) */
|
||||
#define BIGGEST_ALIGNMENT 128
|
||||
|
||||
#define MINIMUM_ATOMIC_ALIGNMENT 128
|
||||
|
||||
/* Make all static objects 16-byte aligned. This allows us to assume
|
||||
they are also padded to 16-bytes, which means we can use a single
|
||||
load or store instruction to access them. Do the same for objects
|
||||
on the stack. (Except a bug (?) allows some stack objects to be
|
||||
unaligned.) */
|
||||
#define DATA_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
|
||||
#define CONSTANT_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
|
||||
#define LOCAL_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
|
||||
|
||||
#define EMPTY_FIELD_BOUNDARY 32
|
||||
|
||||
#define STRICT_ALIGNMENT 1
|
||||
|
||||
/* symbol_ref's of functions are not aligned to 16 byte boundary. */
|
||||
#define ALIGNED_SYMBOL_REF_P(X) \
|
||||
(GET_CODE (X) == SYMBOL_REF \
|
||||
&& (! SYMBOL_REF_FUNCTION_P (X) \
|
||||
|| align_functions >= 16))
|
||||
|
||||
#define PCC_BITFIELD_TYPE_MATTERS 1
|
||||
|
||||
#define MAX_FIXED_MODE_SIZE 128
|
||||
|
||||
#define STACK_SAVEAREA_MODE(save_level) SImode
|
||||
|
||||
#define STACK_SIZE_MODE SImode
|
||||
|
||||
/* #define TARGET_FLOAT_FORMAT SPU_FLOAT_FORMAT */
|
||||
|
||||
#ifndef MODE_HAS_NANS
|
||||
#define MODE_HAS_NANS(MODE) \
|
||||
(FLOAT_MODE_P (MODE) \
|
||||
&& MODE != SFmode \
|
||||
&& !LARGEST_EXPONENT_IS_NORMAL (GET_MODE_BITSIZE (MODE)))
|
||||
#endif
|
||||
|
||||
#ifndef MODE_HAS_INFINITIES
|
||||
#define MODE_HAS_INFINITIES(MODE) \
|
||||
(FLOAT_MODE_P (MODE) \
|
||||
&& MODE != SFmode \
|
||||
&& !LARGEST_EXPONENT_IS_NORMAL (GET_MODE_BITSIZE (MODE)))
|
||||
#endif
|
||||
|
||||
#ifndef MODE_HAS_SIGN_DEPENDENT_ROUNDING
|
||||
#define MODE_HAS_SIGN_DEPENDENT_ROUNDING(MODE) \
|
||||
(FLOAT_MODE_P (MODE) \
|
||||
&& MODE != SFmode \
|
||||
&& !ROUND_TOWARDS_ZERO)
|
||||
#endif
|
||||
|
||||
#define ROUND_TOWARDS_ZERO 1
|
||||
|
||||
/* This is certainly true. Should it be defined? (It wasn't before.) */
|
||||
/* #define LARGEST_EXPONENT_IS_NORMAL(size) (size != 32) */
|
||||
|
||||
|
||||
/* Type Layout */
|
||||
|
||||
#define INT_TYPE_SIZE 32
|
||||
|
||||
#define LONG_TYPE_SIZE 32
|
||||
|
||||
#define LONG_LONG_TYPE_SIZE 64
|
||||
|
||||
#define FLOAT_TYPE_SIZE 32
|
||||
|
||||
#define DOUBLE_TYPE_SIZE 64
|
||||
|
||||
#define LONG_DOUBLE_TYPE_SIZE 64
|
||||
|
||||
#define DEFAULT_SIGNED_CHAR 0
|
||||
|
||||
|
||||
/* Register Basics */
|
||||
|
||||
/* 128-130 are special registers that never appear in assembly code. */
|
||||
#define FIRST_PSEUDO_REGISTER 132
|
||||
|
||||
#define FIXED_REGISTERS { \
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1 \
|
||||
}
|
||||
|
||||
#define CALL_USED_REGISTERS { \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1 \
|
||||
}
|
||||
|
||||
#define CONDITIONAL_REGISTER_USAGE \
|
||||
spu_conditional_register_usage()
|
||||
|
||||
|
||||
/* Values in Registers */
|
||||
|
||||
#define HARD_REGNO_NREGS(REGNO, MODE) \
|
||||
((GET_MODE_BITSIZE(MODE)+MAX_FIXED_MODE_SIZE-1)/MAX_FIXED_MODE_SIZE)
|
||||
|
||||
#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
|
||||
|
||||
#define MODES_TIEABLE_P(MODE1, MODE2) \
|
||||
(GET_MODE_BITSIZE (MODE1) <= MAX_FIXED_MODE_SIZE \
|
||||
&& GET_MODE_BITSIZE (MODE2) <= MAX_FIXED_MODE_SIZE)
|
||||
|
||||
|
||||
/* Register Classes */
|
||||
|
||||
enum reg_class {
|
||||
NO_REGS,
|
||||
GENERAL_REGS,
|
||||
ALL_REGS,
|
||||
LIM_REG_CLASSES
|
||||
};
|
||||
|
||||
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
||||
|
||||
#define REG_CLASS_NAMES \
|
||||
{ "NO_REGS", \
|
||||
"GENERAL_REGS", \
|
||||
"ALL_REGS" \
|
||||
}
|
||||
|
||||
#define REG_CLASS_CONTENTS { \
|
||||
{0, 0, 0, 0, 0}, /* no regs */ \
|
||||
{0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}, /* general regs */ \
|
||||
{0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}} /* all regs */
|
||||
|
||||
#define REGNO_REG_CLASS(REGNO) (GENERAL_REGS)
|
||||
|
||||
#define BASE_REG_CLASS GENERAL_REGS
|
||||
|
||||
#define INDEX_REG_CLASS GENERAL_REGS
|
||||
|
||||
#define REGNO_OK_FOR_BASE_P(regno) \
|
||||
((regno) < FIRST_PSEUDO_REGISTER || (regno > LAST_VIRTUAL_REGISTER && reg_renumber[regno] >= 0))
|
||||
|
||||
#define REGNO_OK_FOR_INDEX_P(regno) \
|
||||
((regno) < FIRST_PSEUDO_REGISTER || (regno > LAST_VIRTUAL_REGISTER && reg_renumber[regno] >= 0))
|
||||
|
||||
#define INT_REG_OK_FOR_INDEX_P(X,STRICT) \
|
||||
((!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X))))
|
||||
#define INT_REG_OK_FOR_BASE_P(X,STRICT) \
|
||||
((!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X))))
|
||||
|
||||
#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
|
||||
|
||||
#define CLASS_MAX_NREGS(CLASS, MODE) \
|
||||
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
||||
|
||||
/* GCC assumes that modes are in the lowpart of a register, which is
|
||||
only true for SPU. */
|
||||
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
|
||||
((GET_MODE_SIZE (FROM) > 4 || GET_MODE_SIZE (TO) > 4) \
|
||||
&& GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
|
||||
|
||||
|
||||
/* Frame Layout */
|
||||
|
||||
#define STACK_GROWS_DOWNWARD
|
||||
|
||||
#define STARTING_FRAME_OFFSET (0)
|
||||
|
||||
#define STACK_POINTER_OFFSET 32
|
||||
|
||||
#define FIRST_PARM_OFFSET(FNDECL) (0)
|
||||
|
||||
#define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant ((FP), -16)
|
||||
|
||||
#define RETURN_ADDR_RTX(COUNT,FP) (spu_return_addr (COUNT, FP))
|
||||
|
||||
/* Should this be defined? Would it simplify our implementation. */
|
||||
/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
|
||||
|
||||
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG(Pmode, LINK_REGISTER_REGNUM)
|
||||
|
||||
|
||||
/* Stack Checking */
|
||||
|
||||
/* We store the Available Stack Size in the second slot of the stack
|
||||
register. We emit stack checking code during the prologue. */
|
||||
#define STACK_CHECK_BUILTIN 1
|
||||
|
||||
|
||||
/* Frame Registers, and other registers */
|
||||
|
||||
#define STACK_POINTER_REGNUM 1
|
||||
|
||||
/* Will be eliminated. */
|
||||
#define FRAME_POINTER_REGNUM 128
|
||||
|
||||
/* This is not specified in any ABI, so could be set to anything. */
|
||||
#define HARD_FRAME_POINTER_REGNUM 127
|
||||
|
||||
/* Will be eliminated. */
|
||||
#define ARG_POINTER_REGNUM 129
|
||||
|
||||
#define STATIC_CHAIN_REGNUM 2
|
||||
|
||||
#define LINK_REGISTER_REGNUM 0
|
||||
|
||||
/* Used to keep track of instructions that have clobbered the hint
|
||||
* buffer. Users can also specify it in inline asm. */
|
||||
#define HBR_REGNUM 130
|
||||
|
||||
/* Used to keep track of enabling and disabling interrupts. */
|
||||
#define INTR_REGNUM 131
|
||||
|
||||
#define MAX_REGISTER_ARGS 72
|
||||
#define FIRST_ARG_REGNUM 3
|
||||
#define LAST_ARG_REGNUM (FIRST_ARG_REGNUM + MAX_REGISTER_ARGS - 1)
|
||||
|
||||
#define MAX_REGISTER_RETURN 72
|
||||
#define FIRST_RETURN_REGNUM 3
|
||||
#define LAST_RETURN_REGNUM (FIRST_RETURN_REGNUM + MAX_REGISTER_RETURN - 1)
|
||||
|
||||
|
||||
/* Elimination */
|
||||
|
||||
#define FRAME_POINTER_REQUIRED 0
|
||||
|
||||
#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) ((DEPTH) = 0)
|
||||
|
||||
#define ELIMINABLE_REGS \
|
||||
{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
||||
{ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
|
||||
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
||||
{FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
|
||||
|
||||
#define CAN_ELIMINATE(FROM,TO) 1
|
||||
|
||||
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
||||
((OFFSET) = spu_initial_elimination_offset((FROM),(TO)))
|
||||
|
||||
|
||||
/* Stack Arguments */
|
||||
|
||||
#define ACCUMULATE_OUTGOING_ARGS 1
|
||||
|
||||
#define REG_PARM_STACK_SPACE(FNDECL) 0
|
||||
|
||||
#define OUTGOING_REG_PARM_STACK_SPACE
|
||||
|
||||
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (0)
|
||||
|
||||
|
||||
/* Register Arguments */
|
||||
|
||||
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
||||
(spu_function_arg((CUM),(MODE),(TYPE),(NAMED)))
|
||||
|
||||
#define CUMULATIVE_ARGS int
|
||||
|
||||
#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
|
||||
((CUM) = 0)
|
||||
|
||||
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
||||
((CUM) += \
|
||||
(TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST ? 1 \
|
||||
: (MODE) == BLKmode ? ((int_size_in_bytes(TYPE)+15) / 16) \
|
||||
: (MODE) == VOIDmode ? 1 \
|
||||
: HARD_REGNO_NREGS(CUM,MODE))
|
||||
|
||||
#define FUNCTION_ARG_PADDING(MODE,TYPE) upward
|
||||
|
||||
#define PAD_VARARGS_DOWN 0
|
||||
|
||||
#define FUNCTION_ARG_REGNO_P(N) ((N) >= (FIRST_ARG_REGNUM) && (N) <= (LAST_ARG_REGNUM))
|
||||
|
||||
/* Undocumented */
|
||||
#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
|
||||
spu_va_start (valist, nextarg)
|
||||
|
||||
|
||||
/* Scalar Return */
|
||||
|
||||
#define FUNCTION_VALUE(VALTYPE, FUNC) \
|
||||
(spu_function_value((VALTYPE),(FUNC)))
|
||||
|
||||
#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_RETURN_REGNUM)
|
||||
|
||||
#define FUNCTION_VALUE_REGNO_P(N) ((N) >= (FIRST_RETURN_REGNUM) && (N) <= (LAST_RETURN_REGNUM))
|
||||
|
||||
|
||||
/* Aggregate Return */
|
||||
|
||||
#define DEFAULT_PCC_STRUCT_RETURN 0
|
||||
|
||||
|
||||
/* Function Entry */
|
||||
|
||||
#define EXIT_IGNORE_STACK 0
|
||||
|
||||
#define EPILOGUE_USES(REGNO) ((REGNO)==1 ? 1 : 0)
|
||||
|
||||
|
||||
/* Profiling */
|
||||
|
||||
/* Nothing, for now. */
|
||||
#define FUNCTION_PROFILER(FILE, LABELNO) \
|
||||
fprintf (FILE, "\t\n")
|
||||
|
||||
|
||||
/* Trampolines */
|
||||
|
||||
#define TRAMPOLINE_SIZE (TARGET_LARGE_MEM ? 20 : 16)
|
||||
|
||||
#define TRAMPOLINE_ALIGNMENT 128
|
||||
|
||||
#define INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT) \
|
||||
spu_initialize_trampoline(TRAMP,FNADDR,CXT)
|
||||
|
||||
|
||||
/* Addressing Modes */
|
||||
|
||||
#define CONSTANT_ADDRESS_P(X) spu_constant_address_p(X)
|
||||
|
||||
#define MAX_REGS_PER_ADDRESS 2
|
||||
|
||||
#ifdef REG_OK_STRICT
|
||||
# define REG_OK_STRICT_FLAG 1
|
||||
#else
|
||||
# define REG_OK_STRICT_FLAG 0
|
||||
#endif
|
||||
|
||||
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
||||
{ if (spu_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
|
||||
goto ADDR; \
|
||||
}
|
||||
|
||||
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
|
||||
{ rtx result = spu_legitimize_address (X, OLDX, MODE); \
|
||||
if (result != NULL_RTX) \
|
||||
{ \
|
||||
(X) = result; \
|
||||
goto WIN; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
|
||||
|
||||
#define LEGITIMATE_CONSTANT_P(X) spu_legitimate_constant_p(X)
|
||||
|
||||
|
||||
/* Costs */
|
||||
|
||||
#define BRANCH_COST spu_branch_cost
|
||||
|
||||
#define SLOW_BYTE_ACCESS 0
|
||||
|
||||
#define MOVE_RATIO 32
|
||||
|
||||
#define NO_FUNCTION_CSE
|
||||
|
||||
|
||||
/* Sections */
|
||||
|
||||
#define TEXT_SECTION_ASM_OP ".text"
|
||||
|
||||
#define DATA_SECTION_ASM_OP ".data"
|
||||
|
||||
#define JUMP_TABLES_IN_TEXT_SECTION 1
|
||||
|
||||
|
||||
/* PIC */
|
||||
#define PIC_OFFSET_TABLE_REGNUM 126
|
||||
|
||||
|
||||
/* File Framework */
|
||||
|
||||
#define ASM_APP_ON ""
|
||||
|
||||
#define ASM_APP_OFF ""
|
||||
|
||||
#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
|
||||
do { fprintf (STREAM, "\t.file\t"); \
|
||||
output_quoted_string (STREAM, NAME); \
|
||||
fprintf (STREAM, "\n"); \
|
||||
} while (0)
|
||||
|
||||
|
||||
/* Uninitialized Data */
|
||||
#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
|
||||
( fputs (".comm ", (FILE)), \
|
||||
assemble_name ((FILE), (NAME)), \
|
||||
fprintf ((FILE), ",%d\n", (ROUNDED)))
|
||||
|
||||
#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
|
||||
( fputs (".lcomm ", (FILE)), \
|
||||
assemble_name ((FILE), (NAME)), \
|
||||
fprintf ((FILE), ",%d\n", (ROUNDED)))
|
||||
|
||||
|
||||
/* Label Output */
|
||||
#define ASM_OUTPUT_LABEL(FILE,NAME) \
|
||||
do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
|
||||
|
||||
#define ASM_OUTPUT_LABELREF(FILE, NAME) \
|
||||
asm_fprintf (FILE, "%U%s", default_strip_name_encoding (NAME))
|
||||
|
||||
#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
|
||||
( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
|
||||
sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
|
||||
|
||||
|
||||
/* Instruction Output */
|
||||
#define REGISTER_NAMES \
|
||||
{"$lr", "$sp", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
|
||||
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", \
|
||||
"$32", "$33", "$34", "$35", "$36", "$37", "$38", "$39", "$40", "$41", "$42", "$43", "$44", "$45", "$46", "$47", \
|
||||
"$48", "$49", "$50", "$51", "$52", "$53", "$54", "$55", "$56", "$57", "$58", "$59", "$60", "$61", "$62", "$63", \
|
||||
"$64", "$65", "$66", "$67", "$68", "$69", "$70", "$71", "$72", "$73", "$74", "$75", "$76", "$77", "$78", "$79", \
|
||||
"$80", "$81", "$82", "$83", "$84", "$85", "$86", "$87", "$88", "$89", "$90", "$91", "$92", "$93", "$94", "$95", \
|
||||
"$96", "$97", "$98", "$99", "$100", "$101", "$102", "$103", "$104", "$105", "$106", "$107", "$108", "$109", "$110", "$111", \
|
||||
"$112", "$113", "$114", "$115", "$116", "$117", "$118", "$119", "$120", "$121", "$122", "$123", "$124", "$125", "$126", "$127", \
|
||||
"$vfp", "$vap", "hbr", "intr" \
|
||||
}
|
||||
|
||||
#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE)
|
||||
|
||||
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
|
||||
print_operand_address (FILE, ADDR)
|
||||
|
||||
#define LOCAL_LABEL_PREFIX "."
|
||||
|
||||
#define USER_LABEL_PREFIX ""
|
||||
|
||||
|
||||
/* Dispatch Tables */
|
||||
|
||||
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
||||
fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
|
||||
|
||||
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
|
||||
fprintf (FILE, "\t.word .L%d\n", VALUE)
|
||||
|
||||
|
||||
/* Alignment Output */
|
||||
|
||||
#define ASM_OUTPUT_ALIGN(FILE,LOG) \
|
||||
do { if (LOG!=0) fprintf (FILE, "\t.align\t%d\n", (LOG)); } while (0)
|
||||
|
||||
|
||||
/* Misc */
|
||||
|
||||
#define CASE_VECTOR_MODE SImode
|
||||
|
||||
#define MOVE_MAX 16
|
||||
|
||||
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) ((INPREC) <= 32 && (OUTPREC) <= (INPREC))
|
||||
|
||||
#define STORE_FLAG_VALUE -1
|
||||
|
||||
#define Pmode SImode
|
||||
|
||||
#define FUNCTION_MODE QImode
|
||||
|
||||
#define NO_IMPLICIT_EXTERN_C 1
|
||||
|
||||
|
||||
|
||||
/* These are set by the cmp patterns and used while expanding
|
||||
conditional branches. */
|
||||
extern GTY(()) rtx spu_compare_op0;
|
||||
extern GTY(()) rtx spu_compare_op1;
|
||||
|
||||
3171
gcc/config/spu/spu.md
Normal file
3171
gcc/config/spu/spu.md
Normal file
File diff suppressed because it is too large
Load diff
50
gcc/config/spu/spu.opt
Normal file
50
gcc/config/spu/spu.opt
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
; Options for the SPU port of the compiler
|
||||
; Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
; This file is free software; you can redistribute it and/or modify it under
|
||||
; the terms of the GNU General Public License as published by the Free
|
||||
; Software Foundation; either version 2 of the License, or (at your option)
|
||||
; any later version.
|
||||
|
||||
; This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
; for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with this file; see the file COPYING. If not, write to the Free
|
||||
; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
; 02110-1301, USA.
|
||||
|
||||
mwarn-reloc
|
||||
Target Report Mask(WARN_RELOC)
|
||||
Emit warnings when run-time relocations are generated
|
||||
|
||||
merror-reloc
|
||||
Target Report Mask(ERROR_RELOC)
|
||||
Emit errors when run-time relocations are generated
|
||||
|
||||
mbranch-cost=
|
||||
Target RejectNegative Joined UInteger Var(spu_branch_cost) Init(20)
|
||||
Specify cost of branches (Default 20)
|
||||
|
||||
msafe-dma
|
||||
Target Report RejectNegative Mask(SAFE_DMA)
|
||||
Make sure loads and stores are not moved past DMA instructions
|
||||
|
||||
munsafe-dma
|
||||
Target Report RejectNegative InverseMask(SAFE_DMA)
|
||||
volatile must be specified on any memory that is effected by DMA
|
||||
|
||||
mbranch-hints
|
||||
Target Report Mask(BRANCH_HINTS)
|
||||
Generate branch hints for branches
|
||||
|
||||
msmall-mem
|
||||
Target Report RejectNegative InverseMask(LARGE_MEM)
|
||||
Generate code for 18 bit addressing
|
||||
|
||||
mlarge-mem
|
||||
Target Report RejectNegative Mask(LARGE_MEM)
|
||||
Generate code for 32 bit addressing
|
||||
|
||||
2846
gcc/config/spu/spu_internals.h
Normal file
2846
gcc/config/spu/spu_internals.h
Normal file
File diff suppressed because it is too large
Load diff
75
gcc/config/spu/spu_intrinsics.h
Normal file
75
gcc/config/spu/spu_intrinsics.h
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
/* Definitions of Synergistic Processing Unit (SPU). */
|
||||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
/* As a special exception, if you include this header file into source files
|
||||
compiled by GCC, this header file does not by itself cause the resulting
|
||||
executable to be covered by the GNU General Public License. This exception
|
||||
does not however invalidate any other reasons why the executable file might be
|
||||
covered by the GNU General Public License. */
|
||||
|
||||
#ifndef _SPU_INTRINSICS_H
|
||||
#define _SPU_INTRINSICS_H
|
||||
|
||||
#define vec_uchar16 __vector unsigned char
|
||||
#define vec_char16 __vector signed char
|
||||
#define vec_ushort8 __vector unsigned short
|
||||
#define vec_short8 __vector signed short
|
||||
#define vec_uint4 __vector unsigned int
|
||||
#define vec_int4 __vector signed int
|
||||
#define vec_ullong2 __vector unsigned long long
|
||||
#define vec_llong2 __vector signed long long
|
||||
#define vec_float4 __vector float
|
||||
#define vec_double2 __vector double
|
||||
|
||||
/* SPU Channel Defines
|
||||
*/
|
||||
#define SPU_RdEventStat 0
|
||||
#define SPU_WrEventMask 1
|
||||
#define SPU_WrEventAck 2
|
||||
#define SPU_RdSigNotify1 3
|
||||
#define SPU_RdSigNotify2 4
|
||||
#define SPU_WrDec 7
|
||||
#define SPU_RdDec 8
|
||||
#define SPU_RdEventStatMask 11
|
||||
#define SPU_RdMachStat 13
|
||||
#define SPU_WrSRR0 14
|
||||
#define SPU_RdSRR0 15
|
||||
#define SPU_WrOutMbox 28
|
||||
#define SPU_RdInMbox 29
|
||||
#define SPU_WrOutIntrMbox 30
|
||||
|
||||
/* MFC Channel Defines.
|
||||
*/
|
||||
#define MFC_WrMSSyncReq 9
|
||||
#define MFC_RdTagMask 12
|
||||
#define MFC_LSA 16
|
||||
#define MFC_EAH 17
|
||||
#define MFC_EAL 18
|
||||
#define MFC_Size 19
|
||||
#define MFC_TagID 20
|
||||
#define MFC_Cmd 21
|
||||
#define MFC_WrTagMask 22
|
||||
#define MFC_WrTagUpdate 23
|
||||
#define MFC_RdTagStat 24
|
||||
#define MFC_RdListStallStat 25
|
||||
#define MFC_WrListStallAck 26
|
||||
#define MFC_RdAtomicStat 27
|
||||
|
||||
#include <spu_internals.h>
|
||||
|
||||
#endif /* _SPU_INTRINSICS_H */
|
||||
270
gcc/config/spu/spu_mfcio.h
Normal file
270
gcc/config/spu/spu_mfcio.h
Normal file
|
|
@ -0,0 +1,270 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
/* As a special exception, if you include this header file into source files
|
||||
compiled by GCC, this header file does not by itself cause the resulting
|
||||
executable to be covered by the GNU General Public License. This exception
|
||||
does not however invalidate any other reasons why the executable file might be
|
||||
covered by the GNU General Public License. */
|
||||
|
||||
#ifndef __SPU_MFCIO_H__
|
||||
#define __SPU_MFCIO_H__ 1
|
||||
|
||||
#include <spu_intrinsics.h>
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/****************************************************************/
|
||||
/* DMA list element structure*/
|
||||
/****************************************************************/
|
||||
|
||||
#ifdef __GNUC__
|
||||
__extension__
|
||||
#endif
|
||||
typedef struct mfc_list_element {
|
||||
uint64_t notify : 1; /** Stall-and-notify bit */
|
||||
uint64_t reserved : 15;
|
||||
uint64_t size : 16; /** Transfer size */
|
||||
uint64_t eal : 32; /** Lower word of effective address */
|
||||
} mfc_list_element_t;
|
||||
|
||||
/****************************************************************/
|
||||
/* DMA max/min size definitions. */
|
||||
/****************************************************************/
|
||||
|
||||
#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
|
||||
#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
|
||||
|
||||
#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
|
||||
#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
|
||||
|
||||
#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
|
||||
#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
|
||||
|
||||
#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
|
||||
#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
|
||||
|
||||
/****************************************************************/
|
||||
/* MFC DMA Command flags which identify classes of operations. */
|
||||
/****************************************************************/
|
||||
/* Note: These flags may be used in conjunction with the base command types
|
||||
(i.e. MFC_PUT_CMD, MFC_PUTR_CMD, MFC_GET_CMD, and MFC_SNDSIG_CMD)
|
||||
to construct the various command permutations.
|
||||
*/
|
||||
|
||||
#define MFC_BARRIER_ENABLE 0x0001
|
||||
#define MFC_FENCE_ENABLE 0x0002
|
||||
#define MFC_LIST_ENABLE 0x0004 /* SPU Only */
|
||||
#define MFC_START_ENABLE 0x0008 /* PU Only */
|
||||
#define MFC_RESULT_ENABLE 0x0010
|
||||
|
||||
/****************************************************************/
|
||||
/* MFC DMA Put Commands */
|
||||
/****************************************************************/
|
||||
|
||||
#define MFC_PUT_CMD 0x0020
|
||||
#define MFC_PUTS_CMD 0x0028 /* PU Only */
|
||||
#define MFC_PUTR_CMD 0x0030
|
||||
#define MFC_PUTF_CMD 0x0022
|
||||
#define MFC_PUTB_CMD 0x0021
|
||||
#define MFC_PUTFS_CMD 0x002A /* PU Only */
|
||||
#define MFC_PUTBS_CMD 0x0029 /* PU Only */
|
||||
#define MFC_PUTRF_CMD 0x0032
|
||||
#define MFC_PUTRB_CMD 0x0031
|
||||
#define MFC_PUTL_CMD 0x0024 /* SPU Only */
|
||||
#define MFC_PUTRL_CMD 0x0034 /* SPU Only */
|
||||
#define MFC_PUTLF_CMD 0x0026 /* SPU Only */
|
||||
#define MFC_PUTLB_CMD 0x0025 /* SPU Only */
|
||||
#define MFC_PUTRLF_CMD 0x0036 /* SPU Only */
|
||||
#define MFC_PUTRLB_CMD 0x0035 /* SPU Only */
|
||||
|
||||
/****************************************************************/
|
||||
/* MFC DMA Get Commands */
|
||||
/****************************************************************/
|
||||
|
||||
#define MFC_GET_CMD 0x0040
|
||||
#define MFC_GETS_CMD 0x0048 /* PU Only */
|
||||
#define MFC_GETF_CMD 0x0042
|
||||
#define MFC_GETB_CMD 0x0041
|
||||
#define MFC_GETFS_CMD 0x004A /* PU Only */
|
||||
#define MFC_GETBS_CMD 0x0049 /* PU Only */
|
||||
#define MFC_GETL_CMD 0x0044 /* SPU Only */
|
||||
#define MFC_GETLF_CMD 0x0046 /* SPU Only */
|
||||
#define MFC_GETLB_CMD 0x0045 /* SPU Only */
|
||||
|
||||
/****************************************************************/
|
||||
/* MFC Synchronization Commands */
|
||||
/****************************************************************/
|
||||
|
||||
#define MFC_SNDSIG_CMD 0x00A0
|
||||
#define MFC_SNDSIGB_CMD 0x00A1
|
||||
#define MFC_SNDSIGF_CMD 0x00A2
|
||||
#define MFC_BARRIER_CMD 0x00C0
|
||||
#define MFC_EIEIO_CMD 0x00C8
|
||||
#define MFC_SYNC_CMD 0x00CC
|
||||
|
||||
/****************************************************************/
|
||||
/* MFC Atomic Commands */
|
||||
/****************************************************************/
|
||||
|
||||
#define MFC_GETLLAR_CMD 0x00D0 /* SPU Only */
|
||||
#define MFC_PUTLLC_CMD 0x00B4 /* SPU Only */
|
||||
#define MFC_PUTLLUC_CMD 0x00B0 /* SPU Only */
|
||||
#define MFC_PUTQLLUC_CMD 0x00B8 /* SPU Only */
|
||||
|
||||
/****************************************************************/
|
||||
/* Channel Defines */
|
||||
/****************************************************************/
|
||||
|
||||
/* Events Defines for channels
|
||||
* 0 (SPU_RdEventStat),
|
||||
* 1 (SPU_WrEventMask), and
|
||||
* 2 (SPU_WrEventAck).
|
||||
*/
|
||||
#define MFC_TAG_STATUS_UPDATE_EVENT 0x00000001
|
||||
#define MFC_LIST_STALL_NOTIFY_EVENT 0x00000002
|
||||
#define MFC_COMMAND_QUEUE_AVAILABLE_EVENT 0x00000008
|
||||
#define MFC_IN_MBOX_AVAILABLE_EVENT 0x00000010
|
||||
#define MFC_DECREMENTER_EVENT 0x00000020
|
||||
#define MFC_OUT_INTR_MBOX_AVAILABLE_EVENT 0x00000040
|
||||
#define MFC_OUT_MBOX_AVAILABLE_EVENT 0x00000080
|
||||
#define MFC_SIGNAL_NOTIFY_2_EVENT 0x00000100
|
||||
#define MFC_SIGNAL_NOTIFY_1_EVENT 0x00000200
|
||||
#define MFC_LLR_LOST_EVENT 0x00000400
|
||||
#define MFC_PRIV_ATTN_EVENT 0x00000800
|
||||
#define MFC_MULTI_SRC_SYNC_EVENT 0x00001000
|
||||
|
||||
/* Tag Status Update defines for channel 23 (MFC_WrTagUpdate) */
|
||||
#define MFC_TAG_UPDATE_IMMEDIATE 0x0
|
||||
#define MFC_TAG_UPDATE_ANY 0x1
|
||||
#define MFC_TAG_UPDATE_ALL 0x2
|
||||
|
||||
/* Atomic Command Status defines for channel 27 (MFC_RdAtomicStat) */
|
||||
#define MFC_PUTLLC_STATUS 0x00000001
|
||||
#define MFC_PUTLLUC_STATUS 0x00000002
|
||||
#define MFC_GETLLAR_STATUS 0x00000004
|
||||
|
||||
|
||||
/****************************************************************/
|
||||
/* Definitions for constructing a 32-bit command word */
|
||||
/* including the transfer and replacement class id and the */
|
||||
/* command opcode. */
|
||||
/****************************************************************/
|
||||
#define MFC_CMD_WORD(_tid, _rid, _cmd) (((_tid)<<24)|((_rid)<<16)|(_cmd))
|
||||
|
||||
|
||||
/* Addressing Utilities */
|
||||
#define mfc_ea2h(ea) (unsigned int)((unsigned long long)(ea)>>32)
|
||||
#define mfc_ea2l(ea) (unsigned int)(ea)
|
||||
#define mfc_hl2ea(h,l) si_to_ullong(si_selb(si_from_uint(h),\
|
||||
si_rotqbyi(si_from_uint(l), -4),\
|
||||
si_fsmbi(0x0f0f)))
|
||||
#define mfc_ceil128(v) (((v) + 127) & ~127)
|
||||
|
||||
/* MFC DMA */
|
||||
#define mfc_put( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUT_CMD))
|
||||
#define mfc_putf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTF_CMD))
|
||||
#define mfc_putb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTB_CMD))
|
||||
#define mfc_get( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GET_CMD))
|
||||
#define mfc_getf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETF_CMD))
|
||||
#define mfc_getb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETB_CMD))
|
||||
|
||||
/* MFC list DMA */
|
||||
#define mfc_putl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTL_CMD))
|
||||
#define mfc_putlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLF_CMD))
|
||||
#define mfc_putlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLB_CMD))
|
||||
#define mfc_getl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETL_CMD))
|
||||
#define mfc_getlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLF_CMD))
|
||||
#define mfc_getlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLB_CMD))
|
||||
|
||||
/* MFC Atomic Update DMA */
|
||||
#define mfc_getllar( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_GETLLAR_CMD))
|
||||
#define mfc_putllc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLC_CMD))
|
||||
#define mfc_putlluc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLUC_CMD))
|
||||
#define mfc_putqlluc(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128,tag,MFC_CMD_WORD(tid,rid,MFC_PUTQLLUC_CMD))
|
||||
|
||||
/* MFC Synchronization Commands */
|
||||
#define mfc_sndsig( ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIG_CMD))
|
||||
#define mfc_sndsigb(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGB_CMD))
|
||||
#define mfc_sndsigf(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGF_CMD))
|
||||
#define mfc_barrier(tag) spu_mfcdma32(0,0,0,tag,MFC_BARRIER_CMD)
|
||||
#define mfc_eieio(tag,tid,rid) spu_mfcdma32(0,0,0,tag,MFC_CMD_WORD(tid,rid,MFC_EIEIO_CMD))
|
||||
#define mfc_sync(tag) spu_mfcdma32(0,0,0,tag,MFC_SYNC_CMD)
|
||||
|
||||
/* DMA Queue */
|
||||
#define mfc_stat_cmd_queue() spu_readchcnt(MFC_Cmd)
|
||||
|
||||
/* MFC Tag-Status */
|
||||
#define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
|
||||
#define mfc_read_tag_mask() spu_readch(MFC_RdTagMask)
|
||||
|
||||
#define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
|
||||
#define mfc_write_tag_update_immediate() mfc_write_tag_update(MFC_TAG_UPDATE_IMMEDIATE)
|
||||
#define mfc_write_tag_update_any() mfc_write_tag_update(MFC_TAG_UPDATE_ANY)
|
||||
#define mfc_write_tag_update_all() mfc_write_tag_update(MFC_TAG_UPDATE_ALL)
|
||||
#define mfc_stat_tag_update() spu_readchcnt(MFC_WrTagUpdate)
|
||||
|
||||
#define mfc_read_tag_status() spu_readch(MFC_RdTagStat)
|
||||
#define mfc_read_tag_status_immediate() (mfc_write_tag_update_immediate(), mfc_read_tag_status())
|
||||
#define mfc_read_tag_status_any() (mfc_write_tag_update_any(), mfc_read_tag_status())
|
||||
#define mfc_read_tag_status_all() (mfc_write_tag_update_all(), mfc_read_tag_status())
|
||||
#define mfc_stat_tag_status() spu_readchcnt(MFC_RdTagStat)
|
||||
|
||||
/* MFC List Stall-and-Notify Tag */
|
||||
#define mfc_read_list_stall_status() spu_readch(MFC_RdListStallStat)
|
||||
#define mfc_stat_list_stall_status() spu_readchcnt(MFC_RdListStallStat)
|
||||
#define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
|
||||
|
||||
/* Atomic DMA */
|
||||
#define mfc_read_atomic_status() spu_readch(MFC_RdAtomicStat)
|
||||
#define mfc_stat_atomic_status() spu_readchcnt(MFC_RdAtomicStat)
|
||||
|
||||
/* MFC Multi-source Synchronization */
|
||||
#define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
|
||||
#define mfc_stat_multi_src_sync_request() spu_readchcnt(MFC_WrMSSyncReq)
|
||||
|
||||
/* SPU Signal */
|
||||
#define spu_read_signal1() spu_readch(SPU_RdSigNotify1)
|
||||
#define spu_stat_signal1() spu_readchcnt(SPU_RdSigNotify1)
|
||||
#define spu_read_signal2() spu_readch(SPU_RdSigNotify2)
|
||||
#define spu_stat_signal2() spu_readchcnt(SPU_RdSigNotify2)
|
||||
|
||||
/* SPU/PPE Mailbox */
|
||||
#define spu_read_in_mbox() spu_readch(SPU_RdInMbox)
|
||||
#define spu_stat_in_mbox() spu_readchcnt(SPU_RdInMbox)
|
||||
#define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
|
||||
#define spu_stat_out_mbox() spu_readchcnt(SPU_WrOutMbox)
|
||||
#define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
|
||||
#define spu_stat_out_intr_mbox() spu_readchcnt(SPU_WrOutIntrMbox)
|
||||
|
||||
/* SPU Decrementer */
|
||||
#define spu_read_decrementer() spu_readch(SPU_RdDec)
|
||||
#define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
|
||||
|
||||
/* SPU Event */
|
||||
#define spu_read_event_status() spu_readch(SPU_RdEventStat)
|
||||
#define spu_stat_event_status() spu_readchcnt(SPU_RdEventStat)
|
||||
#define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
|
||||
#define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
|
||||
#define spu_read_event_mask() spu_readch(SPU_RdEventStatMask)
|
||||
|
||||
/* SPU State Management */
|
||||
#define spu_read_machine_status() spu_readch(SPU_MachStat)
|
||||
#define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
|
||||
#define spu_read_srr0() spu_readch(SPU_RdSRR0)
|
||||
|
||||
#endif /* __SPU_MFCIO_H__ */
|
||||
99
gcc/config/spu/t-spu-elf
Normal file
99
gcc/config/spu/t-spu-elf
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
# Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
#
|
||||
# This file is free software; you can redistribute it and/or modify it under
|
||||
# the terms of the GNU General Public License as published by the Free
|
||||
# Software Foundation; either version 2 of the License, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
# for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this file; see the file COPYING. If not, write to the Free
|
||||
# Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
# 02110-1301, USA.
|
||||
|
||||
|
||||
# Suppress building libgcc1.a
|
||||
LIBGCC1 =
|
||||
CROSS_LIBGCC1 =
|
||||
|
||||
# On SPU __word__ is TImode which is too inefficient and incomplete for
|
||||
# implementing libgcc routines.
|
||||
TARGET_LIBGCC2_CFLAGS = -fPIC -D__word__=SI -mwarn-reloc
|
||||
|
||||
LIB2FUNCS_STATIC_EXTRA = $(srcdir)/config/spu/float_unssidf.c \
|
||||
$(srcdir)/config/spu/float_unsdidf.c
|
||||
|
||||
LIB2ADDEH = $(srcdir)/unwind-dw2.c $(srcdir)/unwind-dw2-fde.c \
|
||||
$(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
|
||||
|
||||
# We want fine grained libraries, so use the new code to build the
|
||||
# floating point emulation libraries.
|
||||
FPBIT = fp-bit.c
|
||||
DPBIT = dp-bit.c
|
||||
|
||||
dp-bit.c: $(srcdir)/config/fp-bit.c $(srcdir)/config/spu/t-spu-elf
|
||||
echo '#undef US_SOFTWARE_GOFAST' > dp-bit.c
|
||||
cat $(srcdir)/config/fp-bit.c >> dp-bit.c
|
||||
|
||||
fp-bit.c: $(srcdir)/config/fp-bit.c $(srcdir)/config/spu/t-spu-elf
|
||||
echo '#define FLOAT' > fp-bit.c
|
||||
echo '#undef US_SOFTWARE_GOFAST' >> fp-bit.c
|
||||
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
|
||||
|
||||
# Don't let CTOR_LIST end up in sdata section.
|
||||
CRTSTUFF_T_CFLAGS =
|
||||
|
||||
#MULTILIB_OPTIONS=mlarge-mem/mtest-abi
|
||||
#MULTILIB_DIRNAMES=large-mem test-abi
|
||||
#MULTILIB_MATCHES=
|
||||
|
||||
# Neither gcc or newlib seem to have a standard way to generate multiple
|
||||
# crt*.o files. So we don't use the standard crt0.o name anymore.
|
||||
|
||||
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o crt1.o crtend1.o
|
||||
|
||||
LIBGCC = stmp-multilib
|
||||
INSTALL_LIBGCC = install-multilib
|
||||
|
||||
# Assemble startup files.
|
||||
$(T)crti.o: $(srcdir)/config/spu/crti.asm $(GCC_PASSES)
|
||||
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
|
||||
-c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/spu/crti.asm
|
||||
|
||||
$(T)crtn.o: $(srcdir)/config/spu/crtn.asm $(GCC_PASSES)
|
||||
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
|
||||
-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/spu/crtn.asm
|
||||
|
||||
$(T)crt1.o: $(srcdir)/config/spu/crt0.c $(GCC_PASSES)
|
||||
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
|
||||
-O2 \
|
||||
-c -o $(T)crt1.o $(srcdir)/config/spu/crt0.c
|
||||
|
||||
$(T)crtend1.o: $(srcdir)/config/spu/crtend.c $(GCC_PASSES)
|
||||
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
|
||||
-O2 \
|
||||
-c -o $(T)crtend1.o $(srcdir)/config/spu/crtend.c
|
||||
|
||||
|
||||
spu.o: $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
|
||||
$(RTL_H) $(REGS_H) hard-reg-set.h \
|
||||
real.h insn-config.h conditions.h insn-attr.h flags.h $(RECOG_H) \
|
||||
$(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \
|
||||
output.h $(BASIC_BLOCK_H) $(INTEGRATE_H) toplev.h $(GGC_H) $(HASHTAB_H) \
|
||||
$(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h cfglayout.h \
|
||||
$(srcdir)/config/spu/spu-protos.h \
|
||||
$(srcdir)/config/spu/spu-builtins.h \
|
||||
$(srcdir)/config/spu/spu-builtins.def
|
||||
|
||||
spu-c.o: $(srcdir)/config/spu/spu-c.c \
|
||||
$(srcdir)/config/spu/spu-protos.h \
|
||||
$(srcdir)/config/spu/spu-builtins.h \
|
||||
$(srcdir)/config/spu/spu-builtins.def \
|
||||
$(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(CPPLIB_H) \
|
||||
$(TM_P_H) c-pragma.h errors.h coretypes.h $(TM_H) insn-codes.h
|
||||
$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/spu/spu-c.c
|
||||
|
||||
38
gcc/config/spu/vec_types.h
Normal file
38
gcc/config/spu/vec_types.h
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/* Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
/* As a special exception, if you include this header file into source files
|
||||
compiled by GCC, this header file does not by itself cause the resulting
|
||||
executable to be covered by the GNU General Public License. This exception
|
||||
does not however invalidate any other reasons why the executable file might be
|
||||
covered by the GNU General Public License. */
|
||||
|
||||
#ifndef _VEC_TYPES_H_
|
||||
#define _VEC_TYPES_H_ 1
|
||||
|
||||
#include <spu_intrinsics.h>
|
||||
|
||||
/* Define additional PowerPC SIMD/Vector Multi-media eXtension
|
||||
* single keyword vector data types for use in mapping VMX code
|
||||
* to the SPU.
|
||||
*/
|
||||
#define vec_bchar16 __vector unsigned char
|
||||
#define vec_bshort8 __vector unsigned short
|
||||
#define vec_pixel8 __vector unsigned short
|
||||
#define vec_bint4 __vector unsigned int
|
||||
|
||||
#endif /* _VEC_TYPES_H_ */
|
||||
3445
gcc/config/spu/vmx2spu.h
Normal file
3445
gcc/config/spu/vmx2spu.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -821,6 +821,9 @@ for GNU/Linux.
|
|||
@item
|
||||
Andrey Slepuhin for assorted AIX hacking.
|
||||
|
||||
@item
|
||||
Trevor Smigiel for contributing the SPU port.
|
||||
|
||||
@item
|
||||
Christopher Smith did the port for Convex machines.
|
||||
|
||||
|
|
|
|||
|
|
@ -2054,8 +2054,8 @@ defined by shared libraries.
|
|||
|
||||
@item naked
|
||||
@cindex function without a prologue/epilogue code
|
||||
Use this attribute on the ARM, AVR, C4x and IP2K ports to indicate that the
|
||||
specified function does not need prologue/epilogue sequences generated by
|
||||
Use this attribute on the ARM, AVR, C4x, IP2K and SPU ports to indicate that
|
||||
the specified function does not need prologue/epilogue sequences generated by
|
||||
the compiler. It is up to the programmer to provide these sequences.
|
||||
|
||||
@item near
|
||||
|
|
@ -3416,6 +3416,12 @@ documentation in the @xref{i386 Variable Attributes}, section.
|
|||
For documentation of @code{altivec} attribute please see the
|
||||
documentation in the @xref{PowerPC Type Attributes}, section.
|
||||
|
||||
@subsection SPU Variable Attributes
|
||||
|
||||
The SPU supports the @code{spu_vector} attribute for variables. For
|
||||
documentation of this attribute please see the documentation in the
|
||||
@xref{SPU Type Attributes}, section.
|
||||
|
||||
@subsection Xstormy16 Variable Attributes
|
||||
|
||||
One attribute is currently defined for xstormy16 configurations:
|
||||
|
|
@ -3795,6 +3801,15 @@ __attribute__((altivec(bool__))) unsigned
|
|||
These attributes mainly are intended to support the @code{__vector},
|
||||
@code{__pixel}, and @code{__bool} AltiVec keywords.
|
||||
|
||||
@anchor{SPU Type Attributes}
|
||||
@subsection SPU Type Attributes
|
||||
|
||||
The SPU supports the @code{spu_vector} attribute for types. This attribute
|
||||
allows one to declare vector data types supported by the Sony/Toshiba/IBM SPU
|
||||
Language Extensions Specification. It is intended to support the
|
||||
@code{__vector} keyword.
|
||||
|
||||
|
||||
@node Inline
|
||||
@section An Inline Function is As Fast As a Macro
|
||||
@cindex inline functions
|
||||
|
|
@ -6157,6 +6172,7 @@ instructions, but allow the compiler to schedule those calls.
|
|||
* MIPS Paired-Single Support::
|
||||
* PowerPC AltiVec Built-in Functions::
|
||||
* SPARC VIS Built-in Functions::
|
||||
* SPU Built-in Functions::
|
||||
@end menu
|
||||
|
||||
@node Alpha Built-in Functions
|
||||
|
|
@ -9736,6 +9752,62 @@ v8qi __builtin_vis_fpmerge (v4qi, v4qi);
|
|||
int64_t __builtin_vis_pdist (v8qi, v8qi, int64_t);
|
||||
@end smallexample
|
||||
|
||||
@node SPU Built-in Functions
|
||||
@subsection SPU Built-in Functions
|
||||
|
||||
GCC provides extensions for the SPU processor as described in the
|
||||
Sony/Toshiba/IBM SPU Language Extensions Specification, which can be
|
||||
found at @uref{http://cell.scei.co.jp/} or
|
||||
@uref{http://www.ibm.com/developerworks/power/cell/}. GCC's
|
||||
implementation differs in several ways.
|
||||
|
||||
@itemize @bullet
|
||||
|
||||
@item
|
||||
The optional extension of specifying vector constants in parentheses is
|
||||
not supported.
|
||||
|
||||
@item
|
||||
A vector initializer requires no cast if the vector constant is of the
|
||||
same type as the variable it is initializing.
|
||||
|
||||
@item
|
||||
If @code{signed} or @code{unsigned} is omitted, the signedness of the
|
||||
vector type is the default signedness of the base type. The default
|
||||
varies depending on the operating system, so a portable program should
|
||||
always specify the signedness.
|
||||
|
||||
@item
|
||||
By default, the keyword @code{__vector} is added. The macro
|
||||
@code{vector} is defined in @code{<spu_intrinsics.h>} and can be
|
||||
undefined.
|
||||
|
||||
@item
|
||||
GCC allows using a @code{typedef} name as the type specifier for a
|
||||
vector type.
|
||||
|
||||
@item
|
||||
For C, overloaded functions are implemented with macros so the following
|
||||
does not work:
|
||||
|
||||
@smallexample
|
||||
spu_add ((vector signed int)@{1, 2, 3, 4@}, foo);
|
||||
@end smallexample
|
||||
|
||||
Since @code{spu_add} is a macro, the vector constant in the example
|
||||
is treated as four separate arguments. Wrap the entire argument in
|
||||
parentheses for this to work.
|
||||
|
||||
@item
|
||||
The extended version of @code{__builtin_expect} is not supported.
|
||||
|
||||
@end itemize
|
||||
|
||||
@emph{Note:} Only the interface descibed in the aforementioned
|
||||
specification is supported. Internally, GCC uses built-in functions to
|
||||
implement the required functionality, but these are not supported and
|
||||
are subject to change without notice.
|
||||
|
||||
@node Target Format Checks
|
||||
@section Format Checks Specific to Particular Target Machines
|
||||
|
||||
|
|
|
|||
|
|
@ -728,6 +728,12 @@ See RS/6000 and PowerPC Options.
|
|||
-mv8plus -mno-v8plus -mvis -mno-vis
|
||||
-threads -pthreads -pthread}
|
||||
|
||||
@emph{SPU Options}
|
||||
@gccoptlist{-mwarn-reloc -merror-reloc @gol
|
||||
-msafe-dma -munsafe-dma @gol
|
||||
-mbranch-hints @gol
|
||||
-msmall-mem -mlarge-mem}
|
||||
|
||||
@emph{System V Options}
|
||||
@gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}}
|
||||
|
||||
|
|
@ -7358,6 +7364,7 @@ platform.
|
|||
* Score Options::
|
||||
* SH Options::
|
||||
* SPARC Options::
|
||||
* SPU Options::
|
||||
* System V Options::
|
||||
* TMS320C3x/C4x Options::
|
||||
* V850 Options::
|
||||
|
|
@ -12781,6 +12788,57 @@ that of libraries supplied with it.
|
|||
This is a synonym for @option{-pthreads}.
|
||||
@end table
|
||||
|
||||
@node SPU Options
|
||||
@subsection SPU Options
|
||||
@cindex SPU options
|
||||
|
||||
These @samp{-m} options are supported on the SPU:
|
||||
|
||||
@table @gcctabopt
|
||||
@item -mwarn-reloc
|
||||
@itemx -merror-reloc
|
||||
@opindex mwarn-reloc
|
||||
@opindex merror-reloc
|
||||
|
||||
The loader for SPU does not handle dynamic relocations. By default, GCC
|
||||
will give an error when it generates code that requires a dynamic
|
||||
relocation. @option{-mno-error-reloc} disables the error,
|
||||
@option{-mwarn-reloc} will generate a warning instead.
|
||||
|
||||
@item -msafe-dma
|
||||
@itemx -munsafe-dma
|
||||
@opindex msafe-dma
|
||||
@opindex munsafe-dma
|
||||
|
||||
Instructions which initiate or test completion of DMA must not be
|
||||
reordered with respect to loads and stores of the memory which is being
|
||||
accessed. Users typically address this problem using the volatile
|
||||
keyword, but that can lead to inefficient code in places where the
|
||||
memory is known to not change. Rather than mark the memory as volatile
|
||||
we treat the DMA instructions as potentially effecting all memory. With
|
||||
@option{-munsafe-dma} users must use the volatile keyword to protect
|
||||
memory accesses.
|
||||
|
||||
@item -mbranch-hints
|
||||
@opindex mbranch-hints
|
||||
|
||||
By default, GCC will generate a branch hint instruction to avoid
|
||||
pipeline stalls for always taken or probably taken branches. A hint
|
||||
will not be generated closer than 8 instructions away from its branch.
|
||||
There is little reason to disable them, except for debugging purposes,
|
||||
or to make an object a little bit smaller.
|
||||
|
||||
@item -msmall-mem
|
||||
@itemx -mlarge-mem
|
||||
@opindex msmall-mem
|
||||
@opindex mlarge-mem
|
||||
|
||||
By default, GCC generates code assuming that addresses are never larger
|
||||
than 18 bits. With @option{-mlarge-mem} code is generated that assumes
|
||||
a full 32 bit address.
|
||||
|
||||
@end table
|
||||
|
||||
@node System V Options
|
||||
@subsection Options for System V
|
||||
|
||||
|
|
|
|||
|
|
@ -2630,6 +2630,76 @@ Vector zero
|
|||
|
||||
@end table
|
||||
|
||||
@item SPU---@file{config/spu/spu.h}
|
||||
@table @code
|
||||
@item a
|
||||
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
|
||||
|
||||
@item c
|
||||
An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
|
||||
|
||||
@item d
|
||||
An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
|
||||
|
||||
@item f
|
||||
An immediate which can be loaded with @code{fsmbi}.
|
||||
|
||||
@item A
|
||||
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
|
||||
|
||||
@item B
|
||||
An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
|
||||
|
||||
@item C
|
||||
An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
|
||||
|
||||
@item D
|
||||
An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
|
||||
|
||||
@item I
|
||||
A constant in the range [-64, 63] for shift/rotate instructions.
|
||||
|
||||
@item J
|
||||
An unsigned 7-bit constant for conversion/nop/channel instructions.
|
||||
|
||||
@item K
|
||||
A signed 10-bit constant for most arithmetic instructions.
|
||||
|
||||
@item M
|
||||
A signed 16 bit immediate for @code{stop}.
|
||||
|
||||
@item N
|
||||
An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
|
||||
|
||||
@item O
|
||||
An unsigned 7-bit constant whose 3 least significant bits are 0.
|
||||
|
||||
@item P
|
||||
An unsigned 3-bit constant for 16-byte rotates and shifts
|
||||
|
||||
@item R
|
||||
Call operand, reg, for indirect calls
|
||||
|
||||
@item S
|
||||
Call operand, symbol, for relative calls.
|
||||
|
||||
@item T
|
||||
Call operand, const_int, for absolute calls.
|
||||
|
||||
@item U
|
||||
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
|
||||
|
||||
@item W
|
||||
An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
|
||||
|
||||
@item Y
|
||||
An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
|
||||
|
||||
@item Z
|
||||
An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
|
||||
|
||||
@end table
|
||||
|
||||
@item TMS320C3x/C4x---@file{config/c4x/c4x.h}
|
||||
@table @code
|
||||
@item a
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2006-11-20 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
|
||||
|
||||
* configure.ac (need_64bit_hwint): Need 64bit hwint for SPU.
|
||||
* configure : Rebuilt.
|
||||
|
||||
2006-11-01 Douglas Gregor <doug.gregor@gmail.com>
|
||||
|
||||
* include/cpplib.h (enum c_lang): Add CLK_GNUCXX0X and CLK_CXX0X
|
||||
|
|
|
|||
1
libcpp/configure
vendored
1
libcpp/configure
vendored
|
|
@ -8244,6 +8244,7 @@ case $target in
|
|||
sparc64*-*-* | ultrasparc-*-freebsd* | \
|
||||
sparcv9-*-solaris2* | \
|
||||
sparc-*-solaris2.[789] | sparc-*-solaris2.1[0-9]* | \
|
||||
spu-*-* | \
|
||||
sh[123456789l]*-*-*)
|
||||
need_64bit_hwint=yes ;;
|
||||
i[34567]86-*-linux*)
|
||||
|
|
|
|||
|
|
@ -128,6 +128,7 @@ case $target in
|
|||
sparc64*-*-* | ultrasparc-*-freebsd* | \
|
||||
sparcv9-*-solaris2* | \
|
||||
sparc-*-solaris2.[789] | sparc-*-solaris2.1[0-9]* | \
|
||||
spu-*-* | \
|
||||
sh[123456789l]*-*-*)
|
||||
need_64bit_hwint=yes ;;
|
||||
i[34567]86-*-linux*)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue