From 85c1cb2250016893b1e07cc529fd614bb4cddc40 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Sun, 22 Jun 2014 19:18:05 +0200 Subject: [PATCH] rs6000: Merge ashrsi3 and ashrdi3 From-SVN: r211879 --- gcc/ChangeLog | 9 ++ gcc/config/rs6000/rs6000.md | 210 +++++++++++------------------------- 2 files changed, 72 insertions(+), 147 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 129713562e2..d706772bb80 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2014-06-22 Segher Boessenkool + + * config/rs6000/rs6000.md (ashrsi3, two anonymous define_insns and + define_splits, ashrdi3, *ashrdi3_internal1, *ashrdi3_internal2 and + split, *ashrdi3_internal3 and split): Delete, merge into... + (ashr3): New expander. + (*ashr3, ashr3_dot, ashr3_dot2): New. + (*ashrsi3_64): Fix formatting. Replace "i" by "n". + 2014-06-22 Segher Boessenkool * config/rs6000/rs6000.md (rotlsi3, *rotlsi3_internal2 and split, diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index e0332d256df..4d0b5ae5224 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5007,22 +5007,44 @@ "") -(define_insn "ashrsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] +(define_expand "ashr3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:GPR 2 "reg_or_cint_operand" "")))] + "" +{ + /* The generic code does not generate optimal code for the low word + (it should be a rlwimi and a rot). Until we have target code to + solve this generically, keep this expander. */ + + if (mode == DImode && !TARGET_POWERPC64) + { + if (CONST_INT_P (operands[2])) + { + emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); + DONE; + } + else + FAIL; + } +}) + +(define_insn "*ashr3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] "" "@ - sraw %0,%1,%2 - srawi %0,%1,%h2" + sra %0,%1,%2 + srai %0,%1,%2" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no")]) (define_insn "*ashrsi3_64" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (sign_extend:DI + (sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] + (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] "TARGET_POWERPC64" "@ sraw %0,%1,%2 @@ -5030,50 +5052,53 @@ [(set_attr "type" "shift") (set_attr "var_shift" "yes,no")]) -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) +(define_insn_and_split "*ashr3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] - "" + (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - sraw. %3,%1,%2 - srawi. %3,%1,%h2 + sra. %0,%1,%2 + srai. %0,%1,%2 # #" + "&& reload_completed" + [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no,yes,no") (set_attr "dot" "yes") (set_attr "length" "4,4,8,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (ashiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "" +(define_insn_and_split "*ashr3_dot2" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (ashiftrt:SI (match_dup 1) (match_dup 2)))] - "" + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (ashiftrt:GPR (match_dup 1) + (match_dup 2)))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - sraw. %0,%1,%2 - srawi. %0,%1,%h2 + sra. %0,%1,%2 + srai. %0,%1,%2 # #" + "&& reload_completed" + [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no,yes,no") (set_attr "dot" "yes") @@ -5117,22 +5142,6 @@ rs6000_emit_swrsqrt (operands[0], operands[1]); DONE; }) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ashiftrt:SI (match_dup 1) (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (ashiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - ;; Floating-point insns, excluding normal data motion. We combine the SF/DF ;; modes here, and also add in conditional vsx/power8-vector support to access @@ -7718,99 +7727,6 @@ (const_int 0)))] "") -(define_expand "ashrdi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")))] - "" - " -{ - if (TARGET_POWERPC64) - ; - else if (GET_CODE (operands[2]) == CONST_INT) - { - emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); - DONE; - } - else - FAIL; -}") - -(define_insn "*ashrdi3_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] - "TARGET_POWERPC64" - "@ - srad %0,%1,%2 - sradi %0,%1,%H2" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) - -(define_insn "*ashrdi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] - "TARGET_64BIT" - "@ - srad. %3,%1,%2 - sradi. %3,%1,%H2 - # - #" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") - (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (ashiftrt:DI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*ashrdi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (ashiftrt:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT" - "@ - srad. %0,%1,%2 - sradi. %0,%1,%H2 - # - #" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") - (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ashiftrt:DI (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ashiftrt:DI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_expand "anddi3" [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "")