mmips-cpus.def (74kc, [...]): Add PTF_AVOID_IMADD.
2013-03-25 Steve Ellcey <sellcey@mips.com> * config/mips/mmips-cpus.def (74kc, 74kf2_1, 74kf, 74kf, 74kf1_1, 74kfx, 74kx, 74kf3_2): Add PTF_AVOID_IMADD. * config/mips/mips.c (mips_option_override): Set IMADD default. * config/mips/mips.h (PTF_AVOID_IMADD): New. (ISA_HAS_MADD_MSUB): Remove MIPS16 check. (GENERATE_MADD_MSUB): Remove TUNE_74K check, add MIPS16 check. * config/mips/mips.md (mimadd): New flag for integer madd/msub. * doc/invoke.texi (-mimadd/-mno-imadd): New. From-SVN: r197072
This commit is contained in:
Steve Ellcey
Steve Ellcey
parent
f02296ddb9
commit
855e0d0b07
6 changed files with 61 additions and 16 deletions
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@ -1,3 +1,14 @@
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2013-03-25 Steve Ellcey <sellcey@mips.com>
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* config/mips/mmips-cpus.def (74kc, 74kf2_1, 74kf, 74kf, 74kf1_1,
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74kfx, 74kx, 74kf3_2): Add PTF_AVOID_IMADD.
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* config/mips/mips.c (mips_option_override): Set IMADD default.
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* config/mips/mips.h (PTF_AVOID_IMADD): New.
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(ISA_HAS_MADD_MSUB): Remove MIPS16 check.
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(GENERATE_MADD_MSUB): Remove TUNE_74K check, add MIPS16 check.
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* config/mips/mips.md (mimadd): New flag for integer madd/msub.
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* doc/invoke.texi (-mimadd/-mno-imadd): New.
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2013-03-25 Jeff Law <law@redhat.com>
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* tree-ssa-dom.c (record_equivalences_from_incoming_edge): Rework
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@ -121,13 +121,13 @@ MIPS_CPU ("34kfx", PROCESSOR_24KF1_1, 33, 0)
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MIPS_CPU ("34kx", PROCESSOR_24KF1_1, 33, 0)
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MIPS_CPU ("34kn", PROCESSOR_24KC, 33, 0) /* 34K with MT but no DSP. */
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MIPS_CPU ("74kc", PROCESSOR_74KC, 33, 0) /* 74K with DSPr2. */
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MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, 0)
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MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, 0)
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MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, 0)
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MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, 0)
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MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, 0)
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MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, 0)
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MIPS_CPU ("74kc", PROCESSOR_74KC, 33, PTF_AVOID_IMADD) /* 74K with DSPr2. */
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MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD)
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MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD)
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MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD)
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MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD)
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MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD)
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MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, PTF_AVOID_IMADD)
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MIPS_CPU ("1004kc", PROCESSOR_24KC, 33, 0) /* 1004K with MT/DSP. */
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MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, 33, 0)
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@ -16912,6 +16912,21 @@ mips_option_override (void)
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warning (0, "the %qs architecture does not support branch-likely"
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" instructions", mips_arch_info->name);
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/* If the user hasn't specified -mimadd or -mno-imadd set
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MASK_IMADD based on the target architecture and tuning
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flags. */
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if ((target_flags_explicit & MASK_IMADD) == 0)
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{
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if (ISA_HAS_MADD_MSUB &&
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(mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
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target_flags |= MASK_IMADD;
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else
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target_flags &= ~MASK_IMADD;
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}
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else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
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warning (0, "the %qs architecture does not support madd or msub"
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" instructions", mips_arch_info->name);
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/* The effect of -mabicalls isn't defined for the EABI. */
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if (mips_abi == ABI_EABI && TARGET_ABICALLS)
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{
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@ -47,8 +47,15 @@ extern int target_flags_explicit;
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PTF_AVOID_BRANCHLIKELY
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Set if it is usually not profitable to use branch-likely instructions
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for this target, typically because the branches are always predicted
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taken and so incur a large overhead when not taken. */
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#define PTF_AVOID_BRANCHLIKELY 0x1
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taken and so incur a large overhead when not taken.
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PTF_AVOID_IMADD
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Set if it is usually not profitable to use the integer MADD or MSUB
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instructions because of the overhead of getting the result out of
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the HI/LO registers. */
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#define PTF_AVOID_BRANCHLIKELY 0x1
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#define PTF_AVOID_IMADD 0x2
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/* Information about one recognized processor. Defined here for the
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benefit of TARGET_CPU_CPP_BUILTINS. */
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@ -874,14 +881,13 @@ struct mips_cpu_info {
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&& !TARGET_MIPS16)
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/* ISA has integer multiply-accumulate instructions, madd and msub. */
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#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
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|| ISA_MIPS32R2 \
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|| ISA_MIPS64 \
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|| ISA_MIPS64R2) \
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&& !TARGET_MIPS16)
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#define ISA_HAS_MADD_MSUB (ISA_MIPS32 \
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|| ISA_MIPS32R2 \
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|| ISA_MIPS64 \
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|| ISA_MIPS64R2)
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/* Integer multiply-accumulate instructions should be generated. */
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#define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
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#define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
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/* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
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#define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
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@ -58,6 +58,10 @@ mmad
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Target Report Var(TARGET_MAD)
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Use PMC-style 'mad' instructions
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mimadd
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Target Report Mask(IMADD)
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Use integer madd/msub instructions
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march=
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Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value)
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-march=ISA Generate code for the given ISA
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@ -766,7 +766,7 @@ Objective-C and Objective-C++ Dialects}.
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-mcheck-zero-division -mno-check-zero-division @gol
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-mdivide-traps -mdivide-breaks @gol
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-mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol
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-mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol
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-mmad -mno-mad -mimadd -mno-imadd -mfused-madd -mno-fused-madd -nocpp @gol
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-mfix-24k -mno-fix-24k @gol
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-mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol
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-mfix-r10000 -mno-fix-r10000 -mfix-vr4120 -mno-fix-vr4120 @gol
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@ -16481,6 +16481,15 @@ This option has no effect on abicalls code. The default is
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Enable (disable) use of the @code{mad}, @code{madu} and @code{mul}
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instructions, as provided by the R4650 ISA@.
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@item -mimadd
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@itemx -mno-imadd
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@opindex mimadd
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@opindex mno-imadd
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Enable (disable) use of the @code{madd} and @code{msub} integer
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instructions. The default is @option{-mimadd} on architectures
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that support @code{madd} and @code{msub} except for the 74k
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architecture where it was found to generate slower code.
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@item -mfused-madd
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@itemx -mno-fused-madd
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@opindex mfused-madd
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