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* config/c4x/c4x.md: Fix comment.

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From-SVN: r83898
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Steven Bosscher 2004-06-30 09:32:41 +00:00
parent badd64ad92
commit 852a13111d
2 changed files with 8 additions and 18 deletions
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8
gcc/ChangeLog
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@ -1,4 +1,8 @@
2004-0630 Akos Kiss <akiss@inf.u-szeged.hu>
2004-06-30 Steven Bosscher <stevenb@suse.de>
* config/c4x/c4x.md: Fix comment.
2004-06-30 Akos Kiss <akiss@inf.u-szeged.hu>
* arm.md (cond_return_inverted): Add "length" attribute.
@ -4861,7 +4865,7 @@
2004-05-22 Zack Weinberg <zack@codesourcery.com>
* tree.h (struct tree_decl): Add possibly_inlined bit.
* tree.h (struct tree_decl): Add possibly_inlined bit.
(DECL_POSSIBLY_INLINED): New accessor macro.
* cgraph.h: Remove declaration of cgraph_inline_hash.
* cgraph.c: Remove definition of cgraph_inline_hash.

18
gcc/config/c4x/c4x.md
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@ -474,31 +474,17 @@
])
;
; C4x FUNCTIONAL UNITS
;
; Define functional units for instruction scheduling to minimize
; pipeline conflicts.
; C4x PIPELINE MODEL
;
; With the C3x, an external memory write (with no wait states) takes
; two cycles and an external memory read (with no wait states) takes
; one cycle. However, an external read following an external write
; takes two cycles. With internal memory, reads and writes take
; half a cycle.
;
; When a C4x address register is loaded it will not be available for
; an extra machine cycle. Calculating with a C4x address register
; makes it unavailable for 2 machine cycles. To notify GCC of these
; pipeline delays, each of the auxiliary and index registers are declared
; as separate functional units.
; makes it unavailable for 2 machine cycles.
;
; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
;
; MULTIPLICITY 1 (C4x has no independent identical function units)
; SIMULTANEITY 0 (C4x is pipelined)
; READY_DELAY 1 (Results usually ready after every cyle)
; ISSUE_DELAY 1 (Can issue insns every cycle)
; Just some dummy definitions. The real work is done in c4x_adjust_cost.
; These are needed so the min/max READY_DELAY is known.