fixed-bit.c, [...]: Fix comment typos.
* config/fixed-bit.c, config/i386/cpuid.h, config/i386/i386.c, config/i386/i386.md, config/i386/sse.md, function.c, jump.c, modulo-sched.c, ra-conflict.c, toplev.c, tree-eh.c, tree-sra.c, tree-ssa-dse.c, tree-vect-analyze.c, tree-vect-patterns.c, tree-vect-transform.c: Fix comment typos. * doc/extend.texi: Fix a typo. From-SVN: r129291
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
d06a846ba9
commit
84fbffb2c2
18 changed files with 32 additions and 23 deletions
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@ -1,3 +1,12 @@
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2007-10-14 Kazu Hirata <kazu@codesourcery.com>
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* config/fixed-bit.c, config/i386/cpuid.h, config/i386/i386.c,
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config/i386/i386.md, config/i386/sse.md, function.c, jump.c,
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modulo-sched.c, ra-conflict.c, toplev.c, tree-eh.c, tree-sra.c,
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tree-ssa-dse.c, tree-vect-analyze.c, tree-vect-patterns.c,
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tree-vect-transform.c: Fix comment typos.
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* doc/extend.texi: Fix a typo.
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2007-10-13 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/aix53.h: New file.
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@ -465,7 +465,7 @@ FIXED_DIVHELPER (FIXED_C_TYPE a, FIXED_C_TYPE b, word_type satp)
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r = pos_a >> (FIXED_WIDTH - FBITS);
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#endif
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/* Unsigned divide r by pos_b to quo_r. The remanider is in mod. */
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/* Unsigned divide r by pos_b to quo_r. The remainder is in mod. */
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quo_r = (UINT_C_TYPE)r / (UINT_C_TYPE)pos_b;
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mod = (UINT_C_TYPE)r % (UINT_C_TYPE)pos_b;
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quo_s = 0;
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@ -117,7 +117,7 @@ __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
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/* Return cpuid data for requested cpuid level, as found in returned
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eax, ebx, ecx and edx registers. The function checks if cpuid is
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supported and returns 1 for valid cpuid information or 0 for
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unsupported cpuid level. All pointers are requred to be non-null. */
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unsupported cpuid level. All pointers are required to be non-null. */
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static __inline int
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__get_cpuid (unsigned int __level,
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@ -1429,7 +1429,7 @@ unsigned int ix86_tune_features[X86_TUNE_LAST] = {
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replacement is long decoded, so this split helps here as well. */
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m_K6,
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/* X86_TUNE_USE_VECTOR_CONVERTS: Preffer vector packed SSE conversion
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/* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
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from integer to FP. */
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m_AMDFAM10,
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};
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@ -13442,8 +13442,8 @@ ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
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#define PPERM_REV_INV 0x60 /* bit reverse & invert src */
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#define PPERM_ZERO 0x80 /* all 0's */
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#define PPERM_ONES 0xa0 /* all 1's */
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#define PPERM_SIGN 0xc0 /* propigate sign bit */
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#define PPERM_INV_SIGN 0xe0 /* invert & propigate sign */
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#define PPERM_SIGN 0xc0 /* propagate sign bit */
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#define PPERM_INV_SIGN 0xe0 /* invert & propagate sign */
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#define PPERM_SRC1 0x00 /* use first source byte */
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#define PPERM_SRC2 0x10 /* use second source byte */
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@ -24879,7 +24879,7 @@ ix86_expand_round (rtx operand0, rtx operand1)
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/* Validate whether a SSE5 instruction is valid or not.
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OPERANDS is the array of operands.
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NUM is the number of operands.
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USES_OC0 is true if the instruction uses OC0 and provides 4 varients.
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USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
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NUM_MEMORY is the maximum number of memory operands to accept. */
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bool ix86_sse5_valid_op_p (rtx operands[], rtx insn, int num, bool uses_oc0, int num_memory)
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{
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@ -24960,7 +24960,7 @@ bool ix86_sse5_valid_op_p (rtx operands[], rtx insn, int num, bool uses_oc0, int
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else if (num == 4 && num_memory == 2)
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{
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/* If there are two memory operations, we can load one of the memory ops
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into the destination register. This is for optimizating the
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into the destination register. This is for optimizing the
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multiply/add ops, which the combiner has optimized both the multiply
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and the add insns to have a memory operation. We have to be careful
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that the destination doesn't overlap with the inputs. */
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@ -207,7 +207,7 @@
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(UNSPECV_PROLOGUE_USE 14)
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])
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;; Constants to represent pcomtrue/pcomfalse varients
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;; Constants to represent pcomtrue/pcomfalse variants
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(define_constants
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[(PCOM_FALSE 0)
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(PCOM_TRUE 1)
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@ -4840,7 +4840,7 @@
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}
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/* Offload operand of cvtsi2ss and cvtsi2sd into memory for
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!TARGET_INTER_UNIT_CONVERSIONS
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It is neccesary for the patterns to not accept nonemmory operands
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It is necessary for the patterns to not accept nonmemory operands
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as we would optimize out later. */
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else if (!TARGET_INTER_UNIT_CONVERSIONS
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&& TARGET_SSE_MATH && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
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@ -7749,7 +7749,7 @@
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[(set_attr "type" "ssemuladd")
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(set_attr "mode" "TI")])
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;; SSE5 parallel integer mutliply/add instructions for the intrinisics
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;; SSE5 parallel integer multiply/add instructions for the intrinisics
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(define_insn "sse5_pmacsswd"
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[(set (match_operand:V4SI 0 "register_operand" "=x,x,x")
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(ss_plus:V4SI
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@ -8143,7 +8143,7 @@ v2di __builtin_ia32_pshlq (v2di, v2di)
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v8hi __builtin_ia32_pshlw (v8hi, v8hi)
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@end smallexample
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The following builtin-in functions are avaialble when @option{-msse5}
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The following builtin-in functions are available when @option{-msse5}
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is used. The second argument must be an integer constant and generate
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the machine instruction that is part of the name with the @samp{_imm}
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suffix removed.
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@ -5702,7 +5702,7 @@ match_asm_constraints_1 (rtx insn, rtx *p_sets, int noutputs)
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asm ("" : "=r" (output), "=m" (input) : "0" (input))
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Here 'input' is used in two occurences as input (once for the
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Here 'input' is used in two occurrences as input (once for the
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input operand, once for the address in the second output operand).
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If we would replace only the occurence of the input operand (to
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make the matching) we would be left with this:
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@ -5714,7 +5714,7 @@ match_asm_constraints_1 (rtx insn, rtx *p_sets, int noutputs)
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value, but different pseudos) where we formerly had only one.
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With more complicated asms this might lead to reload failures
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which wouldn't have happen without this pass. So, iterate over
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all operands and replace all occurences of the register used. */
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all operands and replace all occurrences of the register used. */
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for (j = 0; j < noutputs; j++)
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if (!rtx_equal_p (SET_DEST (p_sets[j]), input)
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&& reg_overlap_mentioned_p (input, SET_DEST (p_sets[j])))
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@ -975,7 +975,7 @@ mark_jump_label (rtx x, rtx insn, int in_mem)
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(insn != NULL && x == PATTERN (insn) && JUMP_P (insn)));
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}
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/* Worker function for mark_jump_label. IN_MEM is TRUE when X occurrs
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/* Worker function for mark_jump_label. IN_MEM is TRUE when X occurs
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within a (MEM ...). IS_TARGET is TRUE when X is to be treated as a
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jump-target; when the JUMP_LABEL field of INSN should be set or a
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REG_LABEL_TARGET note should be added, not a REG_LABEL_OPERAND
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@ -1760,7 +1760,7 @@ ps_insert_empty_row (partial_schedule_ptr ps, int split_row,
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/* Given U_NODE which is the node that failed to be scheduled; LOW and
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UP which are the boundaries of it's scheduling window; compute using
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SCHED_NODES and II a row in the partial schedule that can be splitted
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SCHED_NODES and II a row in the partial schedule that can be split
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which will separate a critical predecessor from a critical successor
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thereby expanding the window, and return it. */
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static int
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@ -1086,7 +1086,7 @@ global_conflicts (void)
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}
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/* Early clobbers, by definition, need to not only
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clobber the registers that are live accross the insn
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clobber the registers that are live across the insn
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but need to clobber the registers that die within the
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insn. The clobbering for registers live across the
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insn is handled above. */
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@ -2152,7 +2152,7 @@ lang_dependent_init (const char *name)
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void
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target_reinit (void)
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{
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/* Reinitialise RTL backend. */
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/* Reinitialize RTL backend. */
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backend_init_target ();
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/* Reinitialize lang-dependent parts. */
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@ -2173,7 +2173,7 @@ optimize_double_finally (tree one, tree two)
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}
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/* Perform EH refactoring optimizations that are simpler to do when code
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flow has been lowered but EH structurs haven't. */
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flow has been lowered but EH structures haven't. */
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static void
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refactor_eh_r (tree t)
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@ -2876,7 +2876,7 @@ struct bitfield_overlap_info
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};
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/* Return true if a BIT_FIELD_REF<(FLD->parent), BLEN, BPOS>
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expression (refereced as BF below) accesses any of the bits in FLD,
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expression (referenced as BF below) accesses any of the bits in FLD,
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false if it doesn't. If DATA is non-null, its field_len and
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field_pos are filled in such that BIT_FIELD_REF<(FLD->parent),
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field_len, field_pos> (referenced as BFLD below) represents the
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@ -653,7 +653,7 @@ execute_simple_dse (void)
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bitmap_ior_into (variables_loaded,
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LOADED_SYMS (bsi_stmt (bsi)));
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/* Look for statements writting into the write only variables.
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/* Look for statements writing into the write only variables.
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And try to remove them. */
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FOR_EACH_BB (bb)
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@ -2279,7 +2279,7 @@ vect_analyze_group_access (struct data_reference *dr)
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/* Analyze the access pattern of the data-reference DR.
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In case of non-consecutive accesse call vect_analyze_group_access() to
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In case of non-consecutive accesses call vect_analyze_group_access() to
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analyze groups of strided accesses. */
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static bool
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@ -545,7 +545,7 @@ vect_recog_pow_pattern (tree last_stmt, tree *type_in, tree *type_out)
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stmts that constitute the pattern. In this case it will be:
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WIDEN_SUM <x_t, sum_0>
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Note: The widneing-sum idiom is a widening reduction pattern that is
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Note: The widening-sum idiom is a widening reduction pattern that is
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vectorized without preserving all the intermediate results. It
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produces only N/2 (widened) results (by summing up pairs of
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intermediate results) rather than all N results. Therefore, we
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@ -1381,7 +1381,7 @@ vect_get_constant_vectors (slp_tree slp_node, VEC(tree,heap) **vec_oprnds,
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}
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/* Get vectorized defintions from SLP_NODE that contains corresponding
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/* Get vectorized definitions from SLP_NODE that contains corresponding
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vectorized def-stmts. */
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static void
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