LoongArch: Use explicit relocs for addresses only used for one load or store with -mexplicit-relocs=auto and -mcmodel={normal,medium}
In these cases, if we use explicit relocs, we end up with 2
instructions:
pcalau12i t0, %pc_hi20(x)
ld.d t0, t0, %pc_lo12(x)
If we use la.local pseudo-op, in the best scenario (x is in +/- 2MiB
range) we still have 2 instructions:
pcaddi t0, %pcrel_20(x)
ld.d t0, t0, 0
If x is out of the range we'll have 3 instructions. So for these cases
just emit machine instructions with explicit relocs.
gcc/ChangeLog:
* config/loongarch/predicates.md (symbolic_pcrel_operand): New
predicate.
* config/loongarch/loongarch.md (define_peephole2): Optimize
la.local + ld/st to pcalau12i + ld/st if the address is only used
once if -mexplicit-relocs=auto and -mcmodel=normal or medium.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/explicit-relocs-auto-single-load-store.c:
New test.
* gcc.target/loongarch/explicit-relocs-auto-single-load-store-no-anchor.c:
New test.
This commit is contained in:
Xi Ruoyao
parent
95db62f4ad
commit
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4 changed files with 149 additions and 0 deletions
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@ -65,6 +65,7 @@
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UNSPEC_LOAD_FROM_GOT
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UNSPEC_PCALAU12I
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UNSPEC_PCALAU12I_GR
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UNSPEC_ORI_L_LO12
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UNSPEC_LUI_L_HI20
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UNSPEC_LUI_H_LO20
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@ -2297,6 +2298,16 @@
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"pcalau12i\t%0,%%pc_hi20(%1)"
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[(set_attr "type" "move")])
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;; @pcalau12i may be used for sibcall so it has a strict constraint. This
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;; allows any general register as the operand.
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(define_insn "@pcalau12i_gr<mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(unspec:P [(match_operand:P 1 "symbolic_operand" "")]
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UNSPEC_PCALAU12I_GR))]
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""
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"pcalau12i\t%0,%%pc_hi20(%1)"
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[(set_attr "type" "move")])
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(define_insn "@ori_l_lo12<mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(unspec:P [(match_operand:P 1 "register_operand" "r")
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@ -3748,6 +3759,117 @@
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[(set_attr "type" "unknown")
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(set_attr "mode" "<MODE>")])
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;; With normal or medium code models, if the only use of a pc-relative
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;; address is for loading or storing a value, then relying on linker
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;; relaxation is not better than emitting the machine instruction directly.
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;; Even if the la.local pseudo op can be relaxed, we get:
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;;
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;; pcaddi $t0, %pcrel_20(x)
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;; ld.d $t0, $t0, 0
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;;
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;; There are still two instructions, same as using the machine instructions
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;; and explicit relocs:
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;;
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;; pcalau12i $t0, %pc_hi20(x)
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;; ld.d $t0, $t0, %pc_lo12(x)
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;;
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;; And if the pseudo op cannot be relaxed, we'll get a worse result (with
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;; 3 instructions).
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(define_peephole2
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[(set (match_operand:P 0 "register_operand")
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(match_operand:P 1 "symbolic_pcrel_operand"))
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(set (match_operand:GPR 2 "register_operand")
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(mem:GPR (match_dup 0)))]
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"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
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&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
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&& (peep2_reg_dead_p (2, operands[0]) \
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|| REGNO (operands[0]) == REGNO (operands[2]))"
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[(set (match_dup 2) (mem:GPR (lo_sum:P (match_dup 0) (match_dup 1))))]
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{
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emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
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})
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(define_peephole2
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[(set (match_operand:P 0 "register_operand")
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(match_operand:P 1 "symbolic_pcrel_operand"))
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(set (match_operand:GPR 2 "register_operand")
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(mem:GPR (plus (match_dup 0)
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(match_operand 3 "const_int_operand"))))]
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"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
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&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
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&& (peep2_reg_dead_p (2, operands[0]) \
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|| REGNO (operands[0]) == REGNO (operands[2]))"
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[(set (match_dup 2) (mem:GPR (lo_sum:P (match_dup 0) (match_dup 1))))]
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{
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operands[1] = plus_constant (Pmode, operands[1], INTVAL (operands[3]));
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emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
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})
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(define_peephole2
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[(set (match_operand:P 0 "register_operand")
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(match_operand:P 1 "symbolic_pcrel_operand"))
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(set (match_operand:GPR 2 "register_operand")
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(any_extend:GPR (mem:SUBDI (match_dup 0))))]
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"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
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&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
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&& (peep2_reg_dead_p (2, operands[0]) \
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|| REGNO (operands[0]) == REGNO (operands[2]))"
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[(set (match_dup 2)
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(any_extend:GPR (mem:SUBDI (lo_sum:P (match_dup 0)
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(match_dup 1)))))]
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{
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emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
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})
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(define_peephole2
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[(set (match_operand:P 0 "register_operand")
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(match_operand:P 1 "symbolic_pcrel_operand"))
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(set (match_operand:GPR 2 "register_operand")
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(any_extend:GPR
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(mem:SUBDI (plus (match_dup 0)
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(match_operand 3 "const_int_operand")))))]
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"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
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&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
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&& (peep2_reg_dead_p (2, operands[0]) \
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|| REGNO (operands[0]) == REGNO (operands[2]))"
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[(set (match_dup 2)
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(any_extend:GPR (mem:SUBDI (lo_sum:P (match_dup 0)
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(match_dup 1)))))]
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{
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operands[1] = plus_constant (Pmode, operands[1], INTVAL (operands[3]));
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emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
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})
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(define_peephole2
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[(set (match_operand:P 0 "register_operand")
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(match_operand:P 1 "symbolic_pcrel_operand"))
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(set (mem:QHWD (match_dup 0))
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(match_operand:QHWD 2 "register_operand"))]
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"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
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&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
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&& (peep2_reg_dead_p (2, operands[0])) \
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&& REGNO (operands[0]) != REGNO (operands[2])"
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[(set (mem:QHWD (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
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{
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emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
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})
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(define_peephole2
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[(set (match_operand:P 0 "register_operand")
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(match_operand:P 1 "symbolic_pcrel_operand"))
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(set (mem:QHWD (plus (match_dup 0)
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(match_operand 3 "const_int_operand")))
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(match_operand:QHWD 2 "register_operand"))]
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"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
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&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
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&& (peep2_reg_dead_p (2, operands[0])) \
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&& REGNO (operands[0]) != REGNO (operands[2])"
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[(set (mem:QHWD (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
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{
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operands[1] = plus_constant (Pmode, operands[1], INTVAL (operands[3]));
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emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
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})
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;; Synchronization instructions.
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(include "sync.md")
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@ -563,6 +563,13 @@
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return loongarch_symbolic_constant_p (op, &type);
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})
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(define_predicate "symbolic_pcrel_operand"
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(match_code "const,symbol_ref,label_ref")
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{
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enum loongarch_symbol_type type;
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return loongarch_symbolic_constant_p (op, &type) && type == SYMBOL_PCREL;
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})
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(define_predicate "equality_operator"
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(match_code "eq,ne"))
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@ -0,0 +1,6 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mexplicit-relocs=auto -fno-section-anchors" } */
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#include "explicit-relocs-auto-single-load-store.c"
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/* { dg-final { scan-assembler-not "la.local" } } */
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@ -0,0 +1,14 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mexplicit-relocs=auto" } */
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long a;
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int b;
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unsigned int c;
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long load_a() { return a; }
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long load_b() { return b; }
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long load_c() { return c; }
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void store_a(long x) { a = x; }
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void store_b(int x) { b = x; }
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/* { dg-final { scan-assembler-not "la.local" } } */
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