i386: Clear upper bits of XMM register for V4HFmode/V2HFmode operations [PR110762]
Similar like r14-2786-gade30fad6669e5, the patch is for V4HF/V2HFmode. gcc/ChangeLog: PR target/110762 * config/i386/mmx.md (<insn><mode>3): Changed from define_insn to define_expand and break into .. (<insn>v4hf3): .. this. (divv4hf3): .. this. (<insn>v2hf3): .. this. (divv2hf3): .. this. (movd_v2hf_to_sse): New define_expand. (movq_<mode>_to_sse): Extend to V4HFmode. (mmxdoublevecmode): Ditto. (V2FI_V4HF): New mode iterator. * config/i386/sse.md (*vec_concatv4sf): Extend to hanlde V8HF by using mode iterator V4SF_V8HF, renamed to .. (*vec_concat<mode>): .. this. (*vec_concatv4sf_0): Extend to handle V8HF by using mode iterator V4SF_V8HF, renamed to .. (*vec_concat<mode>_0): .. this. (*vec_concatv8hf_movss): New define_insn. (V4SF_V8HF): New mode iterator. gcc/testsuite/ChangeLog: * gcc.target/i386/pr110762-v4hf.c: New test.
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3 changed files with 177 additions and 29 deletions
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@ -79,9 +79,7 @@
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;; V2S* modes
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(define_mode_iterator V2FI [V2SF V2SI])
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;; 4-byte and 8-byte float16 vector modes
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(define_mode_iterator VHF_32_64 [V4HF V2HF])
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(define_mode_iterator V2FI_V4HF [V2SF V2SI V4HF])
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;; Mapping from integer vector mode to mnemonic suffix
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(define_mode_attr mmxvecsize
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[(V8QI "b") (V4QI "b") (V2QI "b")
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@ -108,7 +106,7 @@
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;; Mapping of vector modes to a vector mode of double size
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(define_mode_attr mmxdoublevecmode
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[(V2SF "V4SF") (V2SI "V4SI")])
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[(V2SF "V4SF") (V2SI "V4SI") (V4HF "V8HF")])
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;; Mapping of vector modes back to the scalar modes
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(define_mode_attr mmxscalarmode
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@ -594,7 +592,7 @@
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(define_expand "movq_<mode>_to_sse"
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[(set (match_operand:<mmxdoublevecmode> 0 "register_operand")
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(vec_concat:<mmxdoublevecmode>
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(match_operand:V2FI 1 "nonimmediate_operand")
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(match_operand:V2FI_V4HF 1 "nonimmediate_operand")
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(match_dup 2)))]
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"TARGET_SSE2"
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"operands[2] = CONST0_RTX (<MODE>mode);")
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@ -1927,21 +1925,94 @@
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn "<insn><mode>3"
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[(set (match_operand:VHF_32_64 0 "register_operand" "=v")
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(plusminusmultdiv:VHF_32_64
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(match_operand:VHF_32_64 1 "register_operand" "<comm>v")
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(match_operand:VHF_32_64 2 "register_operand" "v")))]
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(define_expand "<insn>v4hf3"
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[(set (match_operand:V4HF 0 "register_operand")
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(plusminusmult:V4HF
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(match_operand:V4HF 1 "nonimmediate_operand")
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(match_operand:V4HF 2 "nonimmediate_operand")))]
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"TARGET_AVX512FP16 && TARGET_AVX512VL"
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"v<insn>ph\t{%2, %1, %0|%0, %1, %2}"
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[(set (attr "type")
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(cond [(match_test "<CODE> == MULT")
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(const_string "ssemul")
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(match_test "<CODE> == DIV")
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(const_string "ssediv")]
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(const_string "sseadd")))
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(set_attr "prefix" "evex")
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(set_attr "mode" "V8HF")])
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{
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rtx op2 = gen_reg_rtx (V8HFmode);
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rtx op1 = gen_reg_rtx (V8HFmode);
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rtx op0 = gen_reg_rtx (V8HFmode);
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emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
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emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
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emit_insn (gen_<insn>v8hf3 (op0, op1, op2));
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emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
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DONE;
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})
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(define_expand "divv4hf3"
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[(set (match_operand:V4HF 0 "register_operand")
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(div:V4HF
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(match_operand:V4HF 1 "nonimmediate_operand")
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(match_operand:V4HF 2 "nonimmediate_operand")))]
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"TARGET_AVX512FP16 && TARGET_AVX512VL"
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{
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rtx op2 = gen_reg_rtx (V8HFmode);
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rtx op1 = gen_reg_rtx (V8HFmode);
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rtx op0 = gen_reg_rtx (V8HFmode);
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emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
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rtx tmp = gen_rtx_VEC_CONCAT (V8HFmode, operands[2],
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force_reg (V4HFmode, CONST1_RTX (V4HFmode)));
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emit_insn (gen_rtx_SET (op2, tmp));
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emit_insn (gen_divv8hf3 (op0, op1, op2));
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emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
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DONE;
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})
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(define_expand "movd_v2hf_to_sse"
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[(set (match_operand:V8HF 0 "register_operand")
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(vec_merge:V8HF
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(vec_duplicate:V8HF
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(match_operand:V2HF 1 "nonimmediate_operand"))
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(match_operand:V8HF 2 "reg_or_0_operand")
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(const_int 3)))]
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"TARGET_SSE")
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(define_expand "<insn>v2hf3"
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[(set (match_operand:V2HF 0 "register_operand")
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(plusminusmult:V2HF
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(match_operand:V2HF 1 "nonimmediate_operand")
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(match_operand:V2HF 2 "nonimmediate_operand")))]
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"TARGET_AVX512FP16 && TARGET_AVX512VL"
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{
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rtx op2 = gen_reg_rtx (V8HFmode);
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rtx op1 = gen_reg_rtx (V8HFmode);
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rtx op0 = gen_reg_rtx (V8HFmode);
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emit_insn (gen_movd_v2hf_to_sse (op2, operands[2], CONST0_RTX (V8HFmode)));
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emit_insn (gen_movd_v2hf_to_sse (op1, operands[1], CONST0_RTX (V8HFmode)));
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emit_insn (gen_<insn>v8hf3 (op0, op1, op2));
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emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
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DONE;
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})
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(define_expand "divv2hf3"
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[(set (match_operand:V2HF 0 "register_operand")
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(div:V2HF
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(match_operand:V2HF 1 "nonimmediate_operand")
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(match_operand:V2HF 2 "nonimmediate_operand")))]
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"TARGET_AVX512FP16 && TARGET_AVX512VL"
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{
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rtx op2 = gen_reg_rtx (V8HFmode);
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rtx op1 = gen_reg_rtx (V8HFmode);
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rtx op0 = gen_reg_rtx (V8HFmode);
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emit_insn (gen_movd_v2hf_to_sse (op2, operands[2],
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force_reg (V8HFmode, CONST1_RTX (V8HFmode))));
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emit_insn (gen_movd_v2hf_to_sse (op1, operands[1], CONST0_RTX (V8HFmode)));
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emit_insn (gen_divv8hf3 (op0, op1, op2));
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emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
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DONE;
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})
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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@ -430,6 +430,9 @@
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(define_mode_iterator VFB_512
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[V32HF V16SF V8DF])
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(define_mode_iterator V4SF_V8HF
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[V4SF V8HF])
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(define_mode_iterator VI48_AVX512VL
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[V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")
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V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
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@ -10917,11 +10920,11 @@
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(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
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(set_attr "mode" "V4SF,SF,DI,DI")])
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(define_insn "*vec_concatv4sf"
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[(set (match_operand:V4SF 0 "register_operand" "=x,v,x,v")
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(vec_concat:V4SF
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(match_operand:V2SF 1 "register_operand" " 0,v,0,v")
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(match_operand:V2SF 2 "nonimmediate_operand" " x,v,m,m")))]
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(define_insn "*vec_concat<mode>"
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[(set (match_operand:V4SF_V8HF 0 "register_operand" "=x,v,x,v")
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(vec_concat:V4SF_V8HF
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(match_operand:<ssehalfvecmode> 1 "register_operand" " 0,v,0,v")
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(match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" " x,v,m,m")))]
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"TARGET_SSE"
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"@
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movlhps\t{%2, %0|%0, %2}
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@ -10933,17 +10936,34 @@
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(set_attr "prefix" "orig,maybe_evex,orig,maybe_evex")
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(set_attr "mode" "V4SF,V4SF,V2SF,V2SF")])
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(define_insn "*vec_concatv4sf_0"
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[(set (match_operand:V4SF 0 "register_operand" "=v")
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(vec_concat:V4SF
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(match_operand:V2SF 1 "nonimmediate_operand" "vm")
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(match_operand:V2SF 2 "const0_operand")))]
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(define_insn "*vec_concat<mode>_0"
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[(set (match_operand:V4SF_V8HF 0 "register_operand" "=v")
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(vec_concat:V4SF_V8HF
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(match_operand:<ssehalfvecmode> 1 "nonimmediate_operand" "vm")
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(match_operand:<ssehalfvecmode> 2 "const0_operand")))]
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"TARGET_SSE2"
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"%vmovq\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "DF")])
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(define_insn "*vec_concatv8hf_movss"
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[(set (match_operand:V8HF 0 "register_operand" "=x,v,v")
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(vec_merge:V8HF
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(vec_duplicate:V8HF
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(match_operand:V2HF 2 "nonimmediate_operand" "x,m,v"))
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(match_operand:V8HF 1 "reg_or_0_operand" "0,C,v" )
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(const_int 3)))]
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"TARGET_SSE"
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"@
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movss\t{%2, %0|%0, %2}
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%vmovss\t{%2, %0|%0, %2}
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vmovss\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "noavx,*,avx")
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(set_attr "type" "ssemov")
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(set_attr "prefix" "orig,maybe_vex,maybe_vex")
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(set_attr "mode" "SF")])
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;; Avoid combining registers from different units in a single alternative,
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;; see comment above inline_secondary_memory_needed function in i386.cc
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(define_insn "vec_set<mode>_0"
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57
gcc/testsuite/gcc.target/i386/pr110762-v4hf.c
Normal file
57
gcc/testsuite/gcc.target/i386/pr110762-v4hf.c
Normal file
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@ -0,0 +1,57 @@
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/* PR target/110762 */
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/* { dg-do compile { target { ! ia32 } } } */
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/* { dg-options "-O2 -mavx512fp16 -mavx512vl -dp" } */
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typedef _Float16 v4hf __attribute__((vector_size(8)));
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typedef _Float16 v2hf __attribute__((vector_size(4)));
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v4hf
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foo (v4hf a, v4hf b)
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{
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return a + b;
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}
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v4hf
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foo2 (v4hf a, v4hf b)
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{
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return a - b;
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}
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v4hf
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foo3 (v4hf a, v4hf b)
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{
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return a * b;
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}
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v4hf
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foo1 (v4hf a, v4hf b)
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{
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return a / b;
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}
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v2hf
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foo4 (v2hf a, v2hf b)
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{
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return a + b;
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}
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v2hf
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foo5 (v2hf a, v2hf b)
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{
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return a - b;
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}
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v2hf
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foo6 (v2hf a, v2hf b)
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{
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return a * b;
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}
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v2hf
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foo7 (v2hf a, v2hf b)
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{
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return a / b;
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}
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/* { dg-final { scan-assembler-times "\\*vec_concatv8hf_0" 7 } } */
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/* { dg-final { scan-assembler-times "\\*vec_concatv8hf_movss" 8 } } */
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