procyberian/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

i386.md: Remove empty predicates and/or constraints.

Browse source 
* config/i386/i386.md: Remove empty predicates and/or constraints.
	* config/i386/sync.md: Ditto.
	* config/i386/sse.md: Ditto.
	* config/i386/mmx.md: Ditto.
	* config/i386/pentium.md: Ditto.
	* config/i386/athlon.md: Ditto.

From-SVN: r185505
This commit is contained in:
Uros Bizjak 2012-03-18 10:14:23 +01:00
parent e555251484
commit 82e86dc6aa
7 changed files with 2175 additions and 2176 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

63
gcc/ChangeLog
View file

@ -1,3 +1,12 @@
2012-03-18 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md: Remove empty predicates and/or constraints.
* config/i386/sync.md: Ditto.
* config/i386/sse.md: Ditto.
* config/i386/mmx.md: Ditto.
* config/i386/pentium.md: Ditto.
* config/i386/athlon.md: Ditto.
2012-03-16 Richard Guenther <rguenther@suse.de>
PR tree-optimization/52603
@ -38,7 +47,7 @@
(vect_is_simple_use): Treat all constants as vec_constant_def.
2012-03-16 Richard Guenther <rguenther@suse.de>
Kai Tietz <ktietz@redhat.com>
Kai Tietz <ktietz@redhat.com>
PR middle-end/48814
* gimplify.c (gimplify_self_mod_expr): Evaluate postfix
@ -131,8 +140,7 @@
2012-03-15 Jakub Jelinek <jakub@redhat.com>
PR target/52568
* config/i386/i386.c (expand_vec_perm_vperm2f128_vblend): New
function.
* config/i386/i386.c (expand_vec_perm_vperm2f128_vblend): New function.
(ix86_expand_vec_perm_const_1): Use it.
PR target/52568
@ -209,8 +217,8 @@
* config.gcc (target_type_format_char): New. Document it. Set it for
arm*-*-* .
* configure.ac (gnu_unique_option): Use target_type_format_char in test.
Comment rationale.
* configure.ac (gnu_unique_option): Use target_type_format_char
in test. Comment rationale.
* configure: Regenerate .
2012-03-15 Jakub Jelinek <jakub@redhat.com>
@ -363,8 +371,7 @@
* configure.ac (gcc_cv_ld_hidden): Remove *-*-solaris2.8*.
(ld_tls_support): Remove Solaris 8 references.
(lwp_dir, lwp_spec): Remove support for alternate thread library.
* acinclude.m4 (gcc_cv_initfini_array): Remove *-*-solaris2.*
tests.
* acinclude.m4 (gcc_cv_initfini_array): Remove *-*-solaris2.* tests.
* configure: Regenerate.
* config.in: Regenerate.
@ -435,8 +442,7 @@
2012-03-14 Martin Jambor <mjambor@suse.cz>
* expr.c (expand_assignment): Use expand_expr with EXPAND_WRITE
when expanding MEM_REFs, MEM_TARGET_REFs and handled_component
bases.
when expanding MEM_REFs, MEM_TARGET_REFs and handled_component bases.
(expand_expr_real_1): Do not handle misalignment if modifier is
EXPAND_WRITE.
@ -451,9 +457,8 @@
2012-03-14 Richard Guenther <rguenther@suse.de>
PR middle-end/52582
* gimple-fold.c (canonicalize_constructor_val): Make sure
we have a cgraph node for a FUNCTION_DECL that comes from
a constructor.
* gimple-fold.c (canonicalize_constructor_val): Make sure we have
a cgraph node for a FUNCTION_DECL that comes from a constructor.
(gimple_get_virt_method_for_binfo): Likewise.
2012-03-14 Richard Guenther <rguenther@suse.de>
@ -647,9 +652,8 @@
* config/i386/i386.c (ix86_option_override_internal): Properly
set ix86_gen_leave and ix86_gen_monitor. Check Pmode == DImode,
instead of TARGET_64BIT, to set ix86_gen_add3, ix86_gen_sub3,
ix86_gen_one_cmpl2, ix86_gen_andsp,
ix86_gen_allocate_stack_worker, ix86_gen_adjust_stack_and_probe
and ix86_gen_probe_stack_range.
ix86_gen_one_cmpl2, ix86_gen_andsp, ix86_gen_allocate_stack_worker,
ix86_gen_adjust_stack_and_probe and ix86_gen_probe_stack_range.
* config/i386/sse.md (sse3_monitor64): Renamed to ...
(sse3_monitor64_<mode>): This.
@ -691,9 +695,8 @@
(alpha*-dec-osf*): Remove.
* configure: Regenerate.
* config/alpha/host-osf.c, config/alpha/osf5.h,
config/alpha/osf5.opt, config/alpha/va_list.h, config/alpha/x-osf:
Remove.
* config/alpha/host-osf.c, config/alpha/osf5.h, config/alpha/osf5.opt,
config/alpha/va_list.h, config/alpha/x-osf: Remove.
* config/alpha/alpha.h (TARGET_LD_BUGGY_LDGP): Remove.
* config/alpha/alpha.c (struct machine_function): Update comment.
@ -784,10 +787,9 @@
2012-03-12 Richard Guenther <rguenther@suse.de>
* tree-sra.c (create_access_replacement): Only rename the
replacement if we can rewrite it into SSA form. Properly
mark register typed replacements that we cannot rewrite
with TREE_ADDRESSABLE.
* tree-sra.c (create_access_replacement): Only rename the replacement
if we can rewrite it into SSA form. Properly mark register typed
replacements that we cannot rewrite with TREE_ADDRESSABLE.
* tree-cfg.c (verify_expr): Fix BIT_FIELD_REF verification
for aggregate or BLKmode results.
@ -802,8 +804,7 @@
2012-02-12 Kirill Yukhin <kirill.yukhin@intel.com>
* doc/invoke.texi: Document -mrtm option.
* common/config/i386/i386-common.c (OPTION_MASK_ISA_RTM_SET):
New.
* common/config/i386/i386-common.c (OPTION_MASK_ISA_RTM_SET): New.
(OPTION_MASK_ISA_RTM_UNSET): Ditto.
(ix86_handle_option): Handle OPT_mrtm.
* config.gcc (i[34567]86-*-*): Add rtmintrin.h and
@ -814,8 +815,8 @@
__RTM__ if needed.
(ix86_target_string): Define -mrtm option.
(PTA_RTM): New.
(ix86_option_override_internal): Extend "corei7-avx" with
RTM option. Handle new option.
(ix86_option_override_internal): Extend "corei7-avx" with RTM option.
Handle new option.
(ix86_valid_target_attribute_inner_p): Add OPT_mrtm.
(ix86_builtins): Add IX86_BUILTIN_XBEGIN, IX86_BUILTIN_XEND,
IX86_BUILTIN_XTEST.
@ -835,15 +836,14 @@
(xtest): Ditto.
(xtest_1): Ditto.
* config/i386/i386.opt (mrtm): New.
* config/i386/immintrin.h: Include rtmintrin.h and
xtestintrin.h.
* config/i386/immintrin.h: Include rtmintrin.h and xtestintrin.h.
* config/i386/rtmintrin.h: New header.
* config/i386/xtestintrin.h: Ditto.
2012-03-12 Tristan Gingold <gingold@adacore.com>
* ginclude/stddef.h: Adjust previous patch. Use __VMS__ instead
of VMS.
* ginclude/stddef.h: Adjust previous patch.
Use __VMS__ instead of VMS.
2012-03-12 Uros Bizjak <ubizjak@gmail.com>
@ -857,8 +857,7 @@
(C Dialect Options): Move -no-integrated-cpp documentation
from here...
(Preprocessor Options): ...to here. Rewrite the description
so it makes more sense, and remove discussion of merging
front ends.
so it makes more sense, and remove discussion of merging front ends.
2012-03-11 H.J. Lu <hongjiu.lu@intel.com>

8
gcc/config/i386/athlon.md
View file

@ -40,7 +40,7 @@
(cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,leave")
(const_string "vector")
(and (eq_attr "type" "push")
(match_operand 1 "memory_operand" ""))
(match_operand 1 "memory_operand"))
(const_string "vector")
(and (eq_attr "type" "fmov")
(and (eq_attr "memory" "load,store")
@ -574,17 +574,17 @@
(define_insn_reservation "athlon_movlpd_load" 0
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "ssemov")
(match_operand:DF 1 "memory_operand" "")))
(match_operand:DF 1 "memory_operand")))
"athlon-direct,athlon-fpload,athlon-fany")
(define_insn_reservation "athlon_movlpd_load_k8" 2
(and (eq_attr "cpu" "k8")
(and (eq_attr "type" "ssemov")
(match_operand:DF 1 "memory_operand" "")))
(match_operand:DF 1 "memory_operand")))
"athlon-direct,athlon-fploadk8,athlon-fstore")
(define_insn_reservation "athlon_movsd_load_generic64" 2
(and (eq_attr "cpu" "generic64")
(and (eq_attr "type" "ssemov")
(match_operand:DF 1 "memory_operand" "")))
(match_operand:DF 1 "memory_operand")))
"athlon-double,athlon-fploadk8,(athlon-fstore+athlon-fmul)")
(define_insn_reservation "athlon_movaps_load_k8" 2
(and (eq_attr "cpu" "k8,generic64")

2714
gcc/config/i386/i386.md
View file

File diff suppressed because it is too large Load diff

244
gcc/config/i386/mmx.md
View file

@ -69,8 +69,8 @@
;; This is essential for maintaining stable calling conventions.
(define_expand "mov<mode>"
[(set (match_operand:MMXMODEI8 0 "nonimmediate_operand" "")
(match_operand:MMXMODEI8 1 "nonimmediate_operand" ""))]
[(set (match_operand:MMXMODEI8 0 "nonimmediate_operand")
(match_operand:MMXMODEI8 1 "nonimmediate_operand"))]
"TARGET_MMX"
{
ix86_expand_vector_move (<MODE>mode, operands);
@ -201,8 +201,8 @@
(set_attr "mode" "DI,DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
(define_expand "movv2sf"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "")
(match_operand:V2SF 1 "nonimmediate_operand" ""))]
[(set (match_operand:V2SF 0 "nonimmediate_operand")
(match_operand:V2SF 1 "nonimmediate_operand"))]
"TARGET_MMX"
{
ix86_expand_vector_move (V2SFmode, operands);
@ -318,8 +318,8 @@
;; %%% This multiword shite has got to go.
(define_split
[(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
(match_operand:MMXMODE 1 "general_operand" ""))]
[(set (match_operand:MMXMODE 0 "nonimmediate_operand")
(match_operand:MMXMODE 1 "general_operand"))]
"!TARGET_64BIT && reload_completed
&& !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0])
|| MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))"
@ -327,7 +327,7 @@
"ix86_split_long_move (operands); DONE;")
(define_expand "push<mode>1"
[(match_operand:MMXMODE 0 "register_operand" "")]
[(match_operand:MMXMODE 0 "register_operand")]
"TARGET_MMX"
{
ix86_expand_push (<MODE>mode, operands[0]);
@ -335,8 +335,8 @@
})
(define_expand "movmisalign<mode>"
[(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
(match_operand:MMXMODE 1 "nonimmediate_operand" ""))]
[(set (match_operand:MMXMODE 0 "nonimmediate_operand")
(match_operand:MMXMODE 1 "nonimmediate_operand"))]
"TARGET_MMX"
{
ix86_expand_vector_move (<MODE>mode, operands);
@ -359,10 +359,10 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "mmx_addv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "")
[(set (match_operand:V2SF 0 "register_operand")
(plus:V2SF
(match_operand:V2SF 1 "nonimmediate_operand" "")
(match_operand:V2SF 2 "nonimmediate_operand" "")))]
(match_operand:V2SF 1 "nonimmediate_operand")
(match_operand:V2SF 2 "nonimmediate_operand")))]
"TARGET_3DNOW"
"ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
@ -377,15 +377,15 @@
(set_attr "mode" "V2SF")])
(define_expand "mmx_subv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "")
(minus:V2SF (match_operand:V2SF 1 "register_operand" "")
(match_operand:V2SF 2 "nonimmediate_operand" "")))]
[(set (match_operand:V2SF 0 "register_operand")
(minus:V2SF (match_operand:V2SF 1 "register_operand")
(match_operand:V2SF 2 "nonimmediate_operand")))]
"TARGET_3DNOW")
(define_expand "mmx_subrv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "")
(minus:V2SF (match_operand:V2SF 2 "register_operand" "")
(match_operand:V2SF 1 "nonimmediate_operand" "")))]
[(set (match_operand:V2SF 0 "register_operand")
(minus:V2SF (match_operand:V2SF 2 "register_operand")
(match_operand:V2SF 1 "nonimmediate_operand")))]
"TARGET_3DNOW")
(define_insn "*mmx_subv2sf3"
@ -401,9 +401,9 @@
(set_attr "mode" "V2SF")])
(define_expand "mmx_mulv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "")
(mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "")
(match_operand:V2SF 2 "nonimmediate_operand" "")))]
[(set (match_operand:V2SF 0 "register_operand")
(mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand")
(match_operand:V2SF 2 "nonimmediate_operand")))]
"TARGET_3DNOW"
"ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
@ -422,10 +422,10 @@
;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
(define_expand "mmx_<code>v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "")
[(set (match_operand:V2SF 0 "register_operand")
(smaxmin:V2SF
(match_operand:V2SF 1 "nonimmediate_operand" "")
(match_operand:V2SF 2 "nonimmediate_operand" "")))]
(match_operand:V2SF 1 "nonimmediate_operand")
(match_operand:V2SF 2 "nonimmediate_operand")))]
"TARGET_3DNOW"
{
if (!flag_finite_math_only)
@ -568,9 +568,9 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "mmx_eqv2sf3"
[(set (match_operand:V2SI 0 "register_operand" "")
(eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "")
(match_operand:V2SF 2 "nonimmediate_operand" "")))]
[(set (match_operand:V2SI 0 "register_operand")
(eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand")
(match_operand:V2SF 2 "nonimmediate_operand")))]
"TARGET_3DNOW"
"ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);")
@ -690,9 +690,9 @@
(set_attr "mode" "DI")])
(define_expand "vec_setv2sf"
[(match_operand:V2SF 0 "register_operand" "")
(match_operand:SF 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
[(match_operand:V2SF 0 "register_operand")
(match_operand:SF 1 "register_operand")
(match_operand 2 "const_int_operand")]
"TARGET_MMX"
{
ix86_expand_vector_set (false, operands[0], operands[1],
@ -740,9 +740,9 @@
(set_attr "mode" "DI,V4SF,SF,SF,SF,SF")])
(define_split
[(set (match_operand:SF 0 "register_operand" "")
[(set (match_operand:SF 0 "register_operand")
(vec_select:SF
(match_operand:V2SF 1 "memory_operand" "")
(match_operand:V2SF 1 "memory_operand")
(parallel [(const_int 1)])))]
"TARGET_MMX && reload_completed"
[(const_int 0)]
@ -753,9 +753,9 @@
})
(define_expand "vec_extractv2sf"
[(match_operand:SF 0 "register_operand" "")
(match_operand:V2SF 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
[(match_operand:SF 0 "register_operand")
(match_operand:V2SF 1 "register_operand")
(match_operand 2 "const_int_operand")]
"TARGET_MMX"
{
ix86_expand_vector_extract (false, operands[0], operands[1],
@ -764,8 +764,8 @@
})
(define_expand "vec_initv2sf"
[(match_operand:V2SF 0 "register_operand" "")
(match_operand 1 "" "")]
[(match_operand:V2SF 0 "register_operand")
(match_operand 1)]
"TARGET_SSE"
{
ix86_expand_vector_init (false, operands[0], operands[1]);
@ -779,10 +779,10 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "mmx_<plusminus_insn><mode>3"
[(set (match_operand:MMXMODEI8 0 "register_operand" "")
[(set (match_operand:MMXMODEI8 0 "register_operand")
(plusminus:MMXMODEI8
(match_operand:MMXMODEI8 1 "nonimmediate_operand" "")
(match_operand:MMXMODEI8 2 "nonimmediate_operand" "")))]
(match_operand:MMXMODEI8 1 "nonimmediate_operand")
(match_operand:MMXMODEI8 2 "nonimmediate_operand")))]
"TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
@ -798,10 +798,10 @@
(set_attr "mode" "DI")])
(define_expand "mmx_<plusminus_insn><mode>3"
[(set (match_operand:MMXMODE12 0 "register_operand" "")
[(set (match_operand:MMXMODE12 0 "register_operand")
(sat_plusminus:MMXMODE12
(match_operand:MMXMODE12 1 "nonimmediate_operand" "")
(match_operand:MMXMODE12 2 "nonimmediate_operand" "")))]
(match_operand:MMXMODE12 1 "nonimmediate_operand")
(match_operand:MMXMODE12 2 "nonimmediate_operand")))]
"TARGET_MMX"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
@ -816,9 +816,9 @@
(set_attr "mode" "DI")])
(define_expand "mmx_mulv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "")
(mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "")
(match_operand:V4HI 2 "nonimmediate_operand" "")))]
[(set (match_operand:V4HI 0 "register_operand")
(mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand")
(match_operand:V4HI 2 "nonimmediate_operand")))]
"TARGET_MMX"
"ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
@ -832,14 +832,14 @@
(set_attr "mode" "DI")])
(define_expand "mmx_smulv4hi3_highpart"
[(set (match_operand:V4HI 0 "register_operand" "")
[(set (match_operand:V4HI 0 "register_operand")
(truncate:V4HI
(lshiftrt:V4SI
(mult:V4SI
(sign_extend:V4SI
(match_operand:V4HI 1 "nonimmediate_operand" ""))
(match_operand:V4HI 1 "nonimmediate_operand"))
(sign_extend:V4SI
(match_operand:V4HI 2 "nonimmediate_operand" "")))
(match_operand:V4HI 2 "nonimmediate_operand")))
(const_int 16))))]
"TARGET_MMX"
"ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
@ -860,14 +860,14 @@
(set_attr "mode" "DI")])
(define_expand "mmx_umulv4hi3_highpart"
[(set (match_operand:V4HI 0 "register_operand" "")
[(set (match_operand:V4HI 0 "register_operand")
(truncate:V4HI
(lshiftrt:V4SI
(mult:V4SI
(zero_extend:V4SI
(match_operand:V4HI 1 "nonimmediate_operand" ""))
(match_operand:V4HI 1 "nonimmediate_operand"))
(zero_extend:V4SI
(match_operand:V4HI 2 "nonimmediate_operand" "")))
(match_operand:V4HI 2 "nonimmediate_operand")))
(const_int 16))))]
"TARGET_SSE || TARGET_3DNOW_A"
"ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
@ -889,16 +889,16 @@
(set_attr "mode" "DI")])
(define_expand "mmx_pmaddwd"
[(set (match_operand:V2SI 0 "register_operand" "")
[(set (match_operand:V2SI 0 "register_operand")
(plus:V2SI
(mult:V2SI
(sign_extend:V2SI
(vec_select:V2HI
(match_operand:V4HI 1 "nonimmediate_operand" "")
(match_operand:V4HI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)])))
(sign_extend:V2SI
(vec_select:V2HI
(match_operand:V4HI 2 "nonimmediate_operand" "")
(match_operand:V4HI 2 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)]))))
(mult:V2SI
(sign_extend:V2SI
@ -935,15 +935,15 @@
(set_attr "mode" "DI")])
(define_expand "mmx_pmulhrwv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "")
[(set (match_operand:V4HI 0 "register_operand")
(truncate:V4HI
(lshiftrt:V4SI
(plus:V4SI
(mult:V4SI
(sign_extend:V4SI
(match_operand:V4HI 1 "nonimmediate_operand" ""))
(match_operand:V4HI 1 "nonimmediate_operand"))
(sign_extend:V4SI
(match_operand:V4HI 2 "nonimmediate_operand" "")))
(match_operand:V4HI 2 "nonimmediate_operand")))
(const_vector:V4SI [(const_int 32768) (const_int 32768)
(const_int 32768) (const_int 32768)]))
(const_int 16))))]
@ -970,15 +970,15 @@
(set_attr "mode" "DI")])
(define_expand "sse2_umulv1siv1di3"
[(set (match_operand:V1DI 0 "register_operand" "")
[(set (match_operand:V1DI 0 "register_operand")
(mult:V1DI
(zero_extend:V1DI
(vec_select:V1SI
(match_operand:V2SI 1 "nonimmediate_operand" "")
(match_operand:V2SI 1 "nonimmediate_operand")
(parallel [(const_int 0)])))
(zero_extend:V1DI
(vec_select:V1SI
(match_operand:V2SI 2 "nonimmediate_operand" "")
(match_operand:V2SI 2 "nonimmediate_operand")
(parallel [(const_int 0)])))))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
@ -1000,10 +1000,10 @@
(set_attr "mode" "DI")])
(define_expand "mmx_<code>v4hi3"
[(set (match_operand:V4HI 0 "register_operand" "")
[(set (match_operand:V4HI 0 "register_operand")
(smaxmin:V4HI
(match_operand:V4HI 1 "nonimmediate_operand" "")
(match_operand:V4HI 2 "nonimmediate_operand" "")))]
(match_operand:V4HI 1 "nonimmediate_operand")
(match_operand:V4HI 2 "nonimmediate_operand")))]
"TARGET_SSE || TARGET_3DNOW_A"
"ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
@ -1019,10 +1019,10 @@
(set_attr "mode" "DI")])
(define_expand "mmx_<code>v8qi3"
[(set (match_operand:V8QI 0 "register_operand" "")
[(set (match_operand:V8QI 0 "register_operand")
(umaxmin:V8QI
(match_operand:V8QI 1 "nonimmediate_operand" "")
(match_operand:V8QI 2 "nonimmediate_operand" "")))]
(match_operand:V8QI 1 "nonimmediate_operand")
(match_operand:V8QI 2 "nonimmediate_operand")))]
"TARGET_SSE || TARGET_3DNOW_A"
"ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
@ -1046,7 +1046,7 @@
"psra<mmxvecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand" "")
(if_then_else (match_operand 2 "const_int_operand")
(const_string "1")
(const_string "0")))
(set_attr "mode" "DI")])
@ -1060,7 +1060,7 @@
"p<vshift><mmxvecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand" "")
(if_then_else (match_operand 2 "const_int_operand")
(const_string "1")
(const_string "0")))
(set_attr "mode" "DI")])
@ -1072,10 +1072,10 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "mmx_eq<mode>3"
[(set (match_operand:MMXMODEI 0 "register_operand" "")
[(set (match_operand:MMXMODEI 0 "register_operand")
(eq:MMXMODEI
(match_operand:MMXMODEI 1 "nonimmediate_operand" "")
(match_operand:MMXMODEI 2 "nonimmediate_operand" "")))]
(match_operand:MMXMODEI 1 "nonimmediate_operand")
(match_operand:MMXMODEI 2 "nonimmediate_operand")))]
"TARGET_MMX"
"ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
@ -1116,10 +1116,10 @@
(set_attr "mode" "DI")])
(define_expand "mmx_<code><mode>3"
[(set (match_operand:MMXMODEI 0 "register_operand" "")
[(set (match_operand:MMXMODEI 0 "register_operand")
(any_logic:MMXMODEI
(match_operand:MMXMODEI 1 "nonimmediate_operand" "")
(match_operand:MMXMODEI 2 "nonimmediate_operand" "")))]
(match_operand:MMXMODEI 1 "nonimmediate_operand")
(match_operand:MMXMODEI 2 "nonimmediate_operand")))]
"TARGET_MMX"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
@ -1258,12 +1258,12 @@
(set_attr "mode" "DI")])
(define_expand "mmx_pinsrw"
[(set (match_operand:V4HI 0 "register_operand" "")
[(set (match_operand:V4HI 0 "register_operand")
(vec_merge:V4HI
(vec_duplicate:V4HI
(match_operand:SI 2 "nonimmediate_operand" ""))
(match_operand:V4HI 1 "register_operand" "")
(match_operand:SI 3 "const_0_to_3_operand" "")))]
(match_operand:SI 2 "nonimmediate_operand"))
(match_operand:V4HI 1 "register_operand")
(match_operand:SI 3 "const_0_to_3_operand")))]
"TARGET_SSE || TARGET_3DNOW_A"
{
operands[2] = gen_lowpart (HImode, operands[2]);
@ -1276,7 +1276,7 @@
(vec_duplicate:V4HI
(match_operand:HI 2 "nonimmediate_operand" "rm"))
(match_operand:V4HI 1 "register_operand" "0")
(match_operand:SI 3 "const_int_operand" "")))]
(match_operand:SI 3 "const_int_operand")))]
"(TARGET_SSE || TARGET_3DNOW_A)
&& ((unsigned) exact_log2 (INTVAL (operands[3]))
< GET_MODE_NUNITS (V4HImode))"
@ -1304,9 +1304,9 @@
(set_attr "mode" "DI")])
(define_expand "mmx_pshufw"
[(match_operand:V4HI 0 "register_operand" "")
(match_operand:V4HI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "const_int_operand" "")]
[(match_operand:V4HI 0 "register_operand")
(match_operand:V4HI 1 "nonimmediate_operand")
(match_operand:SI 2 "const_int_operand")]
"TARGET_SSE || TARGET_3DNOW_A"
{
int mask = INTVAL (operands[2]);
@ -1322,10 +1322,10 @@
[(set (match_operand:V4HI 0 "register_operand" "=y")
(vec_select:V4HI
(match_operand:V4HI 1 "nonimmediate_operand" "ym")
(parallel [(match_operand 2 "const_0_to_3_operand" "")
(match_operand 3 "const_0_to_3_operand" "")
(match_operand 4 "const_0_to_3_operand" "")
(match_operand 5 "const_0_to_3_operand" "")])))]
(parallel [(match_operand 2 "const_0_to_3_operand")
(match_operand 3 "const_0_to_3_operand")
(match_operand 4 "const_0_to_3_operand")
(match_operand 5 "const_0_to_3_operand")])))]
"TARGET_SSE || TARGET_3DNOW_A"
{
int mask = 0;
@ -1385,9 +1385,9 @@
(set_attr "mode" "DI")])
(define_expand "vec_setv2si"
[(match_operand:V2SI 0 "register_operand" "")
(match_operand:SI 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
[(match_operand:V2SI 0 "register_operand")
(match_operand:SI 1 "register_operand")
(match_operand 2 "const_int_operand")]
"TARGET_MMX"
{
ix86_expand_vector_set (false, operands[0], operands[1],
@ -1441,9 +1441,9 @@
(set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
[(set (match_operand:SI 0 "register_operand")
(vec_select:SI
(match_operand:V2SI 1 "memory_operand" "")
(match_operand:V2SI 1 "memory_operand")
(parallel [(const_int 1)])))]
"TARGET_MMX && reload_completed"
[(const_int 0)]
@ -1454,9 +1454,9 @@
})
(define_expand "vec_extractv2si"
[(match_operand:SI 0 "register_operand" "")
(match_operand:V2SI 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
[(match_operand:SI 0 "register_operand")
(match_operand:V2SI 1 "register_operand")
(match_operand 2 "const_int_operand")]
"TARGET_MMX"
{
ix86_expand_vector_extract (false, operands[0], operands[1],
@ -1465,8 +1465,8 @@
})
(define_expand "vec_initv2si"
[(match_operand:V2SI 0 "register_operand" "")
(match_operand 1 "" "")]
[(match_operand:V2SI 0 "register_operand")
(match_operand 1)]
"TARGET_SSE"
{
ix86_expand_vector_init (false, operands[0], operands[1]);
@ -1474,9 +1474,9 @@
})
(define_expand "vec_setv4hi"
[(match_operand:V4HI 0 "register_operand" "")
(match_operand:HI 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
[(match_operand:V4HI 0 "register_operand")
(match_operand:HI 1 "register_operand")
(match_operand 2 "const_int_operand")]
"TARGET_MMX"
{
ix86_expand_vector_set (false, operands[0], operands[1],
@ -1485,9 +1485,9 @@
})
(define_expand "vec_extractv4hi"
[(match_operand:HI 0 "register_operand" "")
(match_operand:V4HI 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
[(match_operand:HI 0 "register_operand")
(match_operand:V4HI 1 "register_operand")
(match_operand 2 "const_int_operand")]
"TARGET_MMX"
{
ix86_expand_vector_extract (false, operands[0], operands[1],
@ -1496,8 +1496,8 @@
})
(define_expand "vec_initv4hi"
[(match_operand:V4HI 0 "register_operand" "")
(match_operand 1 "" "")]
[(match_operand:V4HI 0 "register_operand")
(match_operand 1)]
"TARGET_SSE"
{
ix86_expand_vector_init (false, operands[0], operands[1]);
@ -1505,9 +1505,9 @@
})
(define_expand "vec_setv8qi"
[(match_operand:V8QI 0 "register_operand" "")
(match_operand:QI 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
[(match_operand:V8QI 0 "register_operand")
(match_operand:QI 1 "register_operand")
(match_operand 2 "const_int_operand")]
"TARGET_MMX"
{
ix86_expand_vector_set (false, operands[0], operands[1],
@ -1516,9 +1516,9 @@
})
(define_expand "vec_extractv8qi"
[(match_operand:QI 0 "register_operand" "")
(match_operand:V8QI 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
[(match_operand:QI 0 "register_operand")
(match_operand:V8QI 1 "register_operand")
(match_operand 2 "const_int_operand")]
"TARGET_MMX"
{
ix86_expand_vector_extract (false, operands[0], operands[1],
@ -1527,8 +1527,8 @@
})
(define_expand "vec_initv8qi"
[(match_operand:V8QI 0 "register_operand" "")
(match_operand 1 "" "")]
[(match_operand:V8QI 0 "register_operand")
(match_operand 1)]
"TARGET_SSE"
{
ix86_expand_vector_init (false, operands[0], operands[1]);
@ -1542,15 +1542,15 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "mmx_uavgv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "")
[(set (match_operand:V8QI 0 "register_operand")
(truncate:V8QI
(lshiftrt:V8HI
(plus:V8HI
(plus:V8HI
(zero_extend:V8HI
(match_operand:V8QI 1 "nonimmediate_operand" ""))
(match_operand:V8QI 1 "nonimmediate_operand"))
(zero_extend:V8HI
(match_operand:V8QI 2 "nonimmediate_operand" "")))
(match_operand:V8QI 2 "nonimmediate_operand")))
(const_vector:V8HI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
@ -1594,15 +1594,15 @@
(set_attr "mode" "DI")])
(define_expand "mmx_uavgv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "")
[(set (match_operand:V4HI 0 "register_operand")
(truncate:V4HI
(lshiftrt:V4SI
(plus:V4SI
(plus:V4SI
(zero_extend:V4SI
(match_operand:V4HI 1 "nonimmediate_operand" ""))
(match_operand:V4HI 1 "nonimmediate_operand"))
(zero_extend:V4SI
(match_operand:V4HI 2 "nonimmediate_operand" "")))
(match_operand:V4HI 2 "nonimmediate_operand")))
(const_vector:V4SI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)]))
(const_int 1))))]
@ -1648,9 +1648,9 @@
(set_attr "mode" "DI")])
(define_expand "mmx_maskmovq"
[(set (match_operand:V8QI 0 "memory_operand" "")
(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "")
(match_operand:V8QI 2 "register_operand" "")
[(set (match_operand:V8QI 0 "memory_operand")
(unspec:V8QI [(match_operand:V8QI 1 "register_operand")
(match_operand:V8QI 2 "register_operand")
(match_dup 0)]
UNSPEC_MASKMOV))]
"TARGET_SSE || TARGET_3DNOW_A")

14
gcc/config/i386/pentium.md
View file

@ -47,22 +47,22 @@
(eq_attr "type" "ibr")
(const_string "pv")
(and (eq_attr "type" "ishift")
(match_operand 2 "const_int_operand" ""))
(match_operand 2 "const_int_operand"))
(const_string "pu")
(and (eq_attr "type" "rotate")
(match_operand 2 "const1_operand" ""))
(match_operand 2 "const1_operand"))
(const_string "pu")
(and (eq_attr "type" "ishift1")
(match_operand 1 "const_int_operand" ""))
(match_operand 1 "const_int_operand"))
(const_string "pu")
(and (eq_attr "type" "rotate1")
(match_operand 1 "const1_operand" ""))
(match_operand 1 "const1_operand"))
(const_string "pu")
(and (eq_attr "type" "call")
(match_operand 0 "constant_call_address_operand" ""))
(match_operand 0 "constant_call_address_operand"))
(const_string "pv")
(and (eq_attr "type" "callv")
(match_operand 1 "constant_call_address_operand" ""))
(match_operand 1 "constant_call_address_operand"))
(const_string "pv")
]
(const_string "np")))
@ -167,7 +167,7 @@
(define_insn_reservation "pent_fpstore" 2
(and (eq_attr "cpu" "pentium")
(and (eq_attr "type" "fmov")
(ior (match_operand 1 "immediate_operand" "")
(ior (match_operand 1 "immediate_operand")
(eq_attr "memory" "store"))))
"(pentium-fp+pentium-np)*2")

1232
gcc/config/i386/sse.md
View file

File diff suppressed because it is too large Load diff

76
gcc/config/i386/sync.md
View file

@ -46,7 +46,7 @@
})
(define_insn "*sse2_lfence"
[(set (match_operand:BLK 0 "" "")
[(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
"TARGET_SSE2"
"lfence"
@ -65,7 +65,7 @@
})
(define_insn "*sse_sfence"
[(set (match_operand:BLK 0 "" "")
[(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
"TARGET_SSE || TARGET_3DNOW_A"
"sfence"
@ -84,7 +84,7 @@
})
(define_insn "mfence_sse2"
[(set (match_operand:BLK 0 "" "")
[(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
"TARGET_64BIT || TARGET_SSE2"
"mfence"
@ -94,7 +94,7 @@
(set_attr "memory" "unknown")])
(define_insn "mfence_nosse"
[(set (match_operand:BLK 0 "" "")
[(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
(clobber (reg:CC FLAGS_REG))]
"!(TARGET_64BIT || TARGET_SSE2)"
@ -102,7 +102,7 @@
[(set_attr "memory" "unknown")])
(define_expand "mem_thread_fence"
[(match_operand:SI 0 "const_int_operand" "")] ;; model
[(match_operand:SI 0 "const_int_operand")] ;; model
""
{
/* Unless this is a SEQ_CST fence, the i386 memory model is strong
@ -142,9 +142,9 @@
])
(define_expand "atomic_load<mode>"
[(set (match_operand:ATOMIC 0 "register_operand" "")
(unspec:ATOMIC [(match_operand:ATOMIC 1 "memory_operand" "")
(match_operand:SI 2 "const_int_operand" "")]
[(set (match_operand:ATOMIC 0 "register_operand")
(unspec:ATOMIC [(match_operand:ATOMIC 1 "memory_operand")
(match_operand:SI 2 "const_int_operand")]
UNSPEC_MOVA))]
""
{
@ -200,9 +200,9 @@
})
(define_expand "atomic_store<mode>"
[(set (match_operand:ATOMIC 0 "memory_operand" "")
(unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")]
[(set (match_operand:ATOMIC 0 "memory_operand")
(unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand")
(match_operand:SI 2 "const_int_operand")]
UNSPEC_MOVA))]
""
{
@ -305,14 +305,14 @@
(set_attr "mode" "DI")])
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:QI 0 "register_operand" "") ;; bool success output
(match_operand:SWI124 1 "register_operand" "") ;; oldval output
(match_operand:SWI124 2 "memory_operand" "") ;; memory
(match_operand:SWI124 3 "register_operand" "") ;; expected input
(match_operand:SWI124 4 "register_operand" "") ;; newval input
(match_operand:SI 5 "const_int_operand" "") ;; is_weak
(match_operand:SI 6 "const_int_operand" "") ;; success model
(match_operand:SI 7 "const_int_operand" "")] ;; failure model
[(match_operand:QI 0 "register_operand") ;; bool success output
(match_operand:SWI124 1 "register_operand") ;; oldval output
(match_operand:SWI124 2 "memory_operand") ;; memory
(match_operand:SWI124 3 "register_operand") ;; expected input
(match_operand:SWI124 4 "register_operand") ;; newval input
(match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand") ;; success model
(match_operand:SI 7 "const_int_operand")] ;; failure model
"TARGET_CMPXCHG"
{
emit_insn (gen_atomic_compare_and_swap_single<mode>
@ -332,14 +332,14 @@
(define_mode_attr DCASHMODE [(DI "SI") (TI "DI")])
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:QI 0 "register_operand" "") ;; bool success output
(match_operand:CASMODE 1 "register_operand" "") ;; oldval output
(match_operand:CASMODE 2 "memory_operand" "") ;; memory
(match_operand:CASMODE 3 "register_operand" "") ;; expected input
(match_operand:CASMODE 4 "register_operand" "") ;; newval input
(match_operand:SI 5 "const_int_operand" "") ;; is_weak
(match_operand:SI 6 "const_int_operand" "") ;; success model
(match_operand:SI 7 "const_int_operand" "")] ;; failure model
[(match_operand:QI 0 "register_operand") ;; bool success output
(match_operand:CASMODE 1 "register_operand") ;; oldval output
(match_operand:CASMODE 2 "memory_operand") ;; memory
(match_operand:CASMODE 3 "register_operand") ;; expected input
(match_operand:CASMODE 4 "register_operand") ;; newval input
(match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand") ;; success model
(match_operand:SI 7 "const_int_operand")] ;; failure model
"TARGET_CMPXCHG"
{
if (<MODE>mode == DImode && TARGET_64BIT)
@ -448,7 +448,7 @@
[(set (match_operand:SWI 0 "register_operand" "=<r>")
(unspec_volatile:SWI
[(match_operand:SWI 1 "memory_operand" "+m")
(match_operand:SI 3 "const_int_operand" "")] ;; model
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPECV_XCHG))
(set (match_dup 1)
(plus:SWI (match_dup 1)
@ -461,12 +461,12 @@
;; __sync_fetch_and_add (x, -N) == N into just lock {add,sub,inc,dec}
;; followed by testing of flags instead of lock xadd and comparisons.
(define_peephole2
[(set (match_operand:SWI 0 "register_operand" "")
(match_operand:SWI 2 "const_int_operand" ""))
[(set (match_operand:SWI 0 "register_operand")
(match_operand:SWI 2 "const_int_operand"))
(parallel [(set (match_dup 0)
(unspec_volatile:SWI
[(match_operand:SWI 1 "memory_operand" "")
(match_operand:SI 4 "const_int_operand" "")]
[(match_operand:SWI 1 "memory_operand")
(match_operand:SI 4 "const_int_operand")]
UNSPECV_XCHG))
(set (match_dup 1)
(plus:SWI (match_dup 1)
@ -474,7 +474,7 @@
(clobber (reg:CC FLAGS_REG))])
(set (reg:CCZ FLAGS_REG)
(compare:CCZ (match_dup 0)
(match_operand:SWI 3 "const_int_operand" "")))]
(match_operand:SWI 3 "const_int_operand")))]
"peep2_reg_dead_p (3, operands[0])
&& (unsigned HOST_WIDE_INT) INTVAL (operands[2])
== -(unsigned HOST_WIDE_INT) INTVAL (operands[3])
@ -492,7 +492,7 @@
[(set (reg:CCZ FLAGS_REG)
(compare:CCZ (unspec_volatile:SWI
[(match_operand:SWI 0 "memory_operand" "+m")
(match_operand:SI 3 "const_int_operand" "")]
(match_operand:SI 3 "const_int_operand")]
UNSPECV_XCHG)
(match_operand:SWI 2 "const_int_operand" "i")))
(set (match_dup 0)
@ -521,7 +521,7 @@
[(set (match_operand:SWI 0 "register_operand" "=<r>") ;; output
(unspec_volatile:SWI
[(match_operand:SWI 1 "memory_operand" "+m") ;; memory
(match_operand:SI 3 "const_int_operand" "")] ;; model
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPECV_XCHG))
(set (match_dup 1)
(match_operand:SWI 2 "register_operand" "0"))] ;; input
@ -533,7 +533,7 @@
(unspec_volatile:SWI
[(plus:SWI (match_dup 0)
(match_operand:SWI 1 "nonmemory_operand" "<r><i>"))
(match_operand:SI 2 "const_int_operand" "")] ;; model
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPECV_LOCK))
(clobber (reg:CC FLAGS_REG))]
""
@ -557,7 +557,7 @@
(unspec_volatile:SWI
[(minus:SWI (match_dup 0)
(match_operand:SWI 1 "nonmemory_operand" "<r><i>"))
(match_operand:SI 2 "const_int_operand" "")] ;; model
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPECV_LOCK))
(clobber (reg:CC FLAGS_REG))]
""
@ -581,7 +581,7 @@
(unspec_volatile:SWI
[(any_logic:SWI (match_dup 0)
(match_operand:SWI 1 "nonmemory_operand" "<r><i>"))
(match_operand:SI 2 "const_int_operand" "")] ;; model
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPECV_LOCK))
(clobber (reg:CC FLAGS_REG))]
""