i386.md (*movoi_internal_avx): Emit insn template depending on type attribute.
* config/i386/i386.md (*movoi_internal_avx): Emit insn template depending on type attribute. (*movti_internal): Ditto. (*movtf_internal): Ditto. (*movxf_internal): Ditto. (*movdf_internal): Ditto. (*movsf_internal): Ditto. From-SVN: r196841
This commit is contained in:
parent
7cf34aaeb6
commit
813e003617
2 changed files with 92 additions and 92 deletions
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@ -1,3 +1,13 @@
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2013-03-20 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (*movoi_internal_avx): Emit insn template
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depending on type attribute.
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(*movti_internal): Ditto.
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(*movtf_internal): Ditto.
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(*movxf_internal): Ditto.
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(*movdf_internal): Ditto.
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(*movsf_internal): Ditto.
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2013-03-20 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (*movti_internal): Set prefix attribute to
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@ -1758,12 +1758,12 @@
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(match_operand:OI 1 "vector_move_operand" "C ,xm,x"))]
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"TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (which_alternative)
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switch (get_attr_type (insn))
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{
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case 0:
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case TYPE_SSELOG1:
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return standard_sse_constant_opcode (insn, operands[1]);
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case 1:
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case 2:
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case TYPE_SSEMOV:
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if (misaligned_operand (operands[0], OImode)
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|| misaligned_operand (operands[1], OImode))
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{
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@ -1779,6 +1779,7 @@
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else
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return "vmovdqa\t{%1, %0|%0, %1}";
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}
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default:
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gcc_unreachable ();
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}
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@ -1800,15 +1801,15 @@
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"(TARGET_64BIT || TARGET_SSE)
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (which_alternative)
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switch (get_attr_type (insn))
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{
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case 0:
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case 1:
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case TYPE_MULTI:
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return "#";
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case 2:
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case TYPE_SSELOG1:
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return standard_sse_constant_opcode (insn, operands[1]);
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case 3:
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case 4:
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case TYPE_SSEMOV:
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/* TDmode values are passed as TImode on the stack. Moving them
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to stack may result in unaligned memory access. */
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if (misaligned_operand (operands[0], TImode)
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@ -1826,12 +1827,13 @@
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else
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return "%vmovdqa\t{%1, %0|%0, %1}";
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}
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "isa" "x64,x64,*,*,*")
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(set_attr "type" "*,*,sselog1,ssemov,ssemov")
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(set_attr "type" "multi,multi,sselog1,ssemov,ssemov")
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(set (attr "prefix")
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(if_then_else (eq_attr "type" "sselog1,ssemov")
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(const_string "maybe_vex")
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@ -1914,7 +1916,7 @@
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case TYPE_LEA:
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return "lea{q}\t{%E1, %0|%0, %E1}";
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default:
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case TYPE_IMOV:
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gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
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if (get_attr_mode (insn) == MODE_SI)
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return "mov{l}\t{%k1, %k0|%k0, %k1}";
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@ -1924,6 +1926,9 @@
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return "lea{q}\t{%E1, %0|%0, %E1}";
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else
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return "mov{q}\t{%1, %0|%0, %1}";
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default:
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gcc_unreachable ();
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}
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}
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[(set (attr "isa")
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@ -2018,14 +2023,18 @@
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case TYPE_SSEMOV:
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switch (get_attr_mode (insn))
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{
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case MODE_TI:
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return "%vmovdqa\t{%1, %0|%0, %1}";
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case MODE_V4SF:
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return "%vmovaps\t{%1, %0|%0, %1}";
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case MODE_SI:
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return "%vmovd\t{%1, %0|%0, %1}";
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case MODE_TI:
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return "%vmovdqa\t{%1, %0|%0, %1}";
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case MODE_V4SF:
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return "%vmovaps\t{%1, %0|%0, %1}";
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case MODE_SF:
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return "%vmovss\t{%1, %0|%0, %1}";
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gcc_assert (!TARGET_AVX);
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return "movss\t{%1, %0|%0, %1}";
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default:
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gcc_unreachable ();
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}
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case TYPE_LEA:
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return "lea{l}\t{%E1, %0|%0, %E1}";
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default:
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case TYPE_IMOV:
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gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
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if (ix86_use_lea_for_mov (insn, operands))
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return "lea{l}\t{%E1, %0|%0, %E1}";
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else
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return "mov{l}\t{%1, %0|%0, %1}";
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default:
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gcc_unreachable ();
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}
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}
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[(set (attr "type")
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@ -2631,12 +2643,12 @@
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|| (!TARGET_MEMORY_MISMATCH_STALL
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&& memory_operand (operands[0], TFmode)))"
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{
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switch (which_alternative)
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switch (get_attr_type (insn))
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{
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case 0:
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case TYPE_SSELOG1:
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return standard_sse_constant_opcode (insn, operands[1]);
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case 1:
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case 2:
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case TYPE_SSEMOV:
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/* Handle misaligned load/store since we
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don't have movmisaligntf pattern. */
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if (misaligned_operand (operands[0], TFmode)
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return "%vmovdqa\t{%1, %0|%0, %1}";
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}
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case 3:
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case 4:
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case TYPE_MULTI:
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return "#";
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default:
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@ -2664,7 +2675,7 @@
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}
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}
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[(set_attr "isa" "*,*,*,x64,x64")
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(set_attr "type" "sselog1,ssemov,ssemov,*,*")
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(set_attr "type" "sselog1,ssemov,ssemov,multi,multi")
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(set (attr "prefix")
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(if_then_else (eq_attr "type" "sselog1,ssemov")
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(const_string "maybe_vex")
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|| (!TARGET_MEMORY_MISMATCH_STALL
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&& memory_operand (operands[0], XFmode)))"
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{
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switch (which_alternative)
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switch (get_attr_type (insn))
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{
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case 0:
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case 1:
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case TYPE_FMOV:
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if (which_alternative == 2)
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return standard_80387_constant_opcode (operands[1]);
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return output_387_reg_move (insn, operands);
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case 2:
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return standard_80387_constant_opcode (operands[1]);
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case 3:
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case 4:
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case 5:
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case TYPE_MULTI:
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return "#";
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default:
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|| ((TARGET_64BIT || !TARGET_MEMORY_MISMATCH_STALL)
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&& memory_operand (operands[0], DFmode)))"
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{
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switch (which_alternative)
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switch (get_attr_type (insn))
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{
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case 0:
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case 1:
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case TYPE_FMOV:
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if (which_alternative == 2)
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return standard_80387_constant_opcode (operands[1]);
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return output_387_reg_move (insn, operands);
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case 2:
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return standard_80387_constant_opcode (operands[1]);
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case 3:
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case 4:
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case TYPE_MULTI:
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return "#";
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case 5:
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case 6:
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return "mov{q}\t{%1, %0|%0, %1}";
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case TYPE_IMOV:
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if (get_attr_mode (insn) == MODE_SI)
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return "mov{l}\t{%1, %k0|%k0, %1}";
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else if (which_alternative == 8)
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return "movabs{q}\t{%1, %0|%0, %1}";
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else
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return "mov{q}\t{%1, %0|%0, %1}";
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case 7:
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return "mov{l}\t{%1, %k0|%k0, %1}";
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case 8:
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return "movabs{q}\t{%1, %0|%0, %1}";
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case 9:
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case 13:
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case TYPE_SSELOG1:
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return standard_sse_constant_opcode (insn, operands[1]);
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case 10:
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case 11:
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case 12:
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case 14:
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case 15:
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case 16:
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case 17:
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case 18:
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case TYPE_SSEMOV:
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switch (get_attr_mode (insn))
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{
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case MODE_DF:
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return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
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return "%vmovsd\t{%1, %0|%0, %1}";
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case MODE_V1DF:
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return "%vmovlpd\t{%1, %d0|%d0, %1}";
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case MODE_V4SF:
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return "%vmovaps\t{%1, %0|%0, %1}";
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case MODE_V2DF:
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return "%vmovapd\t{%1, %0|%0, %1}";
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case MODE_V2SF:
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gcc_assert (!TARGET_AVX);
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return "movlps\t{%1, %0|%0, %1}";
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case MODE_V4SF:
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return "%vmovaps\t{%1, %0|%0, %1}";
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case MODE_V1DF:
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gcc_assert (!TARGET_AVX);
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return "movlpd\t{%1, %0|%0, %1}";
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case MODE_DI:
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/* Handle broken assemblers that require movd instead of movq. */
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(eq_attr "alternative" "5,6,8,17,18")
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(const_string "DI")
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/* xorps is one byte shorter for !TARGET_AVX. */
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/* xorps is one byte shorter for non-AVX targets. */
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(eq_attr "alternative" "9,13")
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(cond [(not (match_test "TARGET_SSE2"))
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(const_string "V4SF")
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(const_string "V2DF"))
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/* For architectures resolving dependencies on
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whole SSE registers use APD move to break dependency
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chains, otherwise use short move to avoid extra work.
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whole SSE registers use movapd to break dependency
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chains, otherwise use short move to avoid extra work. */
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movaps encodes one byte shorter for !TARGET_AVX. */
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/* movaps is one byte shorter for non-AVX targets. */
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(eq_attr "alternative" "10,14")
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(cond [(ior (not (match_test "TARGET_SSE2"))
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(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
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(eq_attr "alternative" "11,15")
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(cond [(not (match_test "TARGET_SSE2"))
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(const_string "V2SF")
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(match_test "TARGET_AVX")
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(const_string "DF")
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(match_test "TARGET_SSE_SPLIT_REGS")
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(const_string "V1DF")
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]
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&& standard_sse_constant_p (operands[1]))))
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|| memory_operand (operands[0], SFmode))"
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{
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switch (which_alternative)
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switch (get_attr_type (insn))
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{
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case 0:
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case 1:
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case TYPE_FMOV:
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if (which_alternative == 2)
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return standard_80387_constant_opcode (operands[1]);
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return output_387_reg_move (insn, operands);
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case 2:
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return standard_80387_constant_opcode (operands[1]);
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case 3:
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case 4:
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case TYPE_IMOV:
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return "mov{l}\t{%1, %0|%0, %1}";
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case 5:
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case TYPE_SSELOG1:
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return standard_sse_constant_opcode (insn, operands[1]);
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case 6:
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case 7:
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case 8:
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case TYPE_SSEMOV:
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switch (get_attr_mode (insn))
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{
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case MODE_V4SF:
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return "%vmovaps\t{%1, %0|%0, %1}";
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case MODE_SF:
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if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
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return "vmovss\t{%1, %0, %0|%0, %0, %1}";
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return "%vmovss\t{%1, %0|%0, %1}";
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case MODE_V4SF:
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return "%vmovaps\t{%1, %0|%0, %1}";
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case MODE_SI:
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return "%vmovd\t{%1, %0|%0, %1}";
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default:
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gcc_unreachable ();
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}
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case 9:
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case 10:
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return "%vmovd\t{%1, %0|%0, %1}";
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case 11:
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case 12:
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case 13:
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case 14:
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case 15:
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case TYPE_MMXMOV:
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if (get_attr_mode (insn) == MODE_DI)
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return "movq\t{%1, %0|%0, %1}";
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return "movd\t{%1, %0|%0, %1}";
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Reference in a new issue