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AArch32 Support ORN for DIMode

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[gcc]
	* config/arm/thumb2.md (*iordi_notdi_di): New pattern.
	(*iordi_notzesidi_di): Likewise.
	(*iordi_notsesidi_di): Likewise.

[gcc/testsuite]
	* gcc.target/arm/iordi_notdi-1.c: New test.

From-SVN: r209613
This commit is contained in:
Ian Bolton 2014-04-22 09:50:33 +00:00 • committed by Ian Bolton
parent 46fbb3ebae
commit 80d3417b69
4 changed files with 137 additions and 0 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2014-04-22 Ian Bolton <ian.bolton@arm.com>
* config/arm/thumb2.md (*iordi_notdi_di): New pattern.
(*iordi_notzesidi_di): Likewise.
(*iordi_notsesidi_di): Likewise.
2014-04-22 Ian Bolton <ian.bolton@arm.com>
* config/arm/arm-protos.h (tune_params): New struct members.

73
gcc/config/arm/thumb2.md
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@ -1370,6 +1370,79 @@
(set_attr "type" "alu_reg")]
)
; Constants for op 2 will never be given to these patterns.
(define_insn_and_split "*iordi_notdi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(ior:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
(match_operand:DI 2 "s_register_operand" "r,0")))]
"TARGET_THUMB2"
"#"
"TARGET_THUMB2 && reload_completed"
[(set (match_dup 0) (ior:SI (not:SI (match_dup 1)) (match_dup 2)))
(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
"
{
operands[3] = gen_highpart (SImode, operands[0]);
operands[0] = gen_lowpart (SImode, operands[0]);
operands[4] = gen_highpart (SImode, operands[1]);
operands[1] = gen_lowpart (SImode, operands[1]);
operands[5] = gen_highpart (SImode, operands[2]);
operands[2] = gen_lowpart (SImode, operands[2]);
}"
[(set_attr "length" "8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "multiple")]
)
(define_insn_and_split "*iordi_notzesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(ior:DI (not:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r")))
(match_operand:DI 1 "s_register_operand" "0,?r")))]
"TARGET_THUMB2"
"#"
; (not (zero_extend...)) means operand0 will always be 0xffffffff
"TARGET_THUMB2 && reload_completed"
[(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
(set (match_dup 3) (const_int -1))]
"
{
operands[3] = gen_highpart (SImode, operands[0]);
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
}"
[(set_attr "length" "4,8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "multiple")]
)
(define_insn_and_split "*iordi_notsesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(ior:DI (not:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r")))
(match_operand:DI 1 "s_register_operand" "0,r")))]
"TARGET_THUMB2"
"#"
"TARGET_THUMB2 && reload_completed"
[(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
(set (match_dup 3) (ior:SI (not:SI
(ashiftrt:SI (match_dup 2) (const_int 31)))
(match_dup 4)))]
"
{
operands[3] = gen_highpart (SImode, operands[0]);
operands[0] = gen_lowpart (SImode, operands[0]);
operands[4] = gen_highpart (SImode, operands[1]);
operands[1] = gen_lowpart (SImode, operands[1]);
}"
[(set_attr "length" "8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "multiple")]
)
(define_insn "*orsi_notsi_si"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2014-04-22 Ian Bolton <ian.bolton@arm.com>
* gcc.target/arm/iordi_notdi-1.c: New test.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/aarch64/vrnd_f64_1.c : New file.

54
gcc/testsuite/gcc.target/arm/iordi_notdi-1.c Normal file
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@ -0,0 +1,54 @@
/* { dg-do run } */
/* { dg-options "-O2 -fno-inline --save-temps" } */
extern void abort (void);
typedef long long s64int;
typedef int s32int;
typedef unsigned long long u64int;
typedef unsigned int u32int;
s64int
iordi_notdi (s64int a, s64int b)
{
return (a | ~b);
}
s64int
iordi_notzesidi (s64int a, u32int b)
{
return (a | ~(u64int) b);
}
s64int
iordi_notsesidi (s64int a, s32int b)
{
return (a | ~(s64int) b);
}
int main ()
{
s64int a64 = 0xdeadbeef00000000ll;
s64int b64 = 0x000000004f4f0112ll;
u32int c32 = 0x01124f4f;
s32int d32 = 0xabbaface;
s64int z = iordi_notdi (a64, b64);
if (z != 0xffffffffb0b0feedll)
abort ();
z = iordi_notzesidi (a64, c32);
if (z != 0xfffffffffeedb0b0ll)
abort ();
z = iordi_notsesidi (a64, d32);
if (z != 0xdeadbeef54450531ll)
abort ();
return 0;
}
/* { dg-final { scan-assembler-times "orn\t" 5 { target arm_thumb2 } } } */
/* { dg-final { cleanup-saved-temps } } */