re PR target/59054 (Powerpc -O0 -mcpu=power7 generates sub-optimal code to load 0)
2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/59054 * config/rs6000/rs6000.md (movdi_internal32): Eliminate constraints that would allow DImode into the traditional Altivec registers, but cause undesirable code generation when loading 0 as a constant. (movdi_internal64): Likewise. (cmp<mode>_fpr): Do not use %x for CR register output. (extendsfdf2_fpr): Fix constraints when -mallow-upper-df and -mallow-upper-sf debug switches are used. [gcc/testsuite] 2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/59054 * gcc.target/powerpc/pr59054.c: New test. From-SVN: r204718
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Michael Meissner
Michael Meissner
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4 changed files with 46 additions and 27 deletions
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@ -1,3 +1,15 @@
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2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/59054
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* config/rs6000/rs6000.md (movdi_internal32): Eliminate
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constraints that would allow DImode into the traditional Altivec
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registers, but cause undesirable code generation when loading 0 as
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a constant.
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(movdi_internal64): Likewise.
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(cmp<mode>_fpr): Do not use %x for CR register output.
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(extendsfdf2_fpr): Fix constraints when -mallow-upper-df and
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-mallow-upper-sf debug switches are used.
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2013-11-12 Andrew MacLeod <amacleod@redhat.com>
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* gimple-expr.h (create_tmp_var_name, create_tmp_var_raw,
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@ -5226,7 +5226,7 @@
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"TARGET_<MODE>_FPR"
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"@
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fcmpu %0,%1,%2
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xscmpudp %x0,%x1,%x2"
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xscmpudp %0,%x1,%x2"
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[(set_attr "type" "fpcompare")])
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;; Floating point conversions
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@ -5237,8 +5237,8 @@
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"")
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(define_insn_and_split "*extendsfdf2_fpr"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,wy,?wy,wv")
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(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wz,Z")))]
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
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(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
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"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
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"@
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#
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@ -5360,7 +5360,7 @@
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"TARGET_<MODE>_FPR && TARGET_CMPB"
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"@
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fcpsgn %0,%2,%1
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xscpsgn<VSs> %x0,%x2,%x1"
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xscpsgn<Fvsx> %x0,%x2,%x1"
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[(set_attr "type" "fp")])
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;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
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@ -10081,8 +10081,8 @@
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;; Use of fprs is disparaged slightly otherwise reload prefers to reload
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;; a gpr into a fpr instead of reloading an invalid 'Y' address
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(define_insn "*movdi_internal32"
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[(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
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(match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
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[(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
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(match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
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"! TARGET_POWERPC64
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&& (gpc_reg_operand (operands[0], DImode)
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|| gpc_reg_operand (operands[1], DImode))"
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@ -10093,8 +10093,7 @@
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stfd%U0%X0 %1,%0
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lfd%U1%X1 %0,%1
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fmr %0,%1
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#
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xxlxor %x0,%x0,%x0"
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#"
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[(set_attr_alternative "type"
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[(const_string "store")
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(const_string "load")
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@ -10114,8 +10113,7 @@
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(const_string "fpload_u")
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(const_string "fpload")))
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(const_string "fp")
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(const_string "*")
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(const_string "vecsimple")])])
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(const_string "*")])])
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(define_split
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[(set (match_operand:DI 0 "gpc_reg_operand" "")
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@ -10146,8 +10144,8 @@
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{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
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(define_insn "*movdi_internal64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,?Z,?wv,?wa,r,*h,*h,?wa,r,?*wg,r,?*wm")
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(match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,wv,Z,wa,*h,r,0,O,*wg,r,*wm,r"))]
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[(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")
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(match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]
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"TARGET_POWERPC64
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&& (gpc_reg_operand (operands[0], DImode)
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|| gpc_reg_operand (operands[1], DImode))"
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@ -10161,13 +10159,9 @@
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stfd%U0%X0 %1,%0
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lfd%U1%X1 %0,%1
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fmr %0,%1
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stxsd%U0x %x1,%y0
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lxsd%U1x %x0,%y1
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xxlor %x0,%x1,%x1
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mf%1 %0
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mt%0 %1
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nop
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xxlxor %x0,%x0,%x0
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mftgpr %0,%1
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mffgpr %0,%1
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mfvsrd %0,%x1
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@ -10206,24 +10200,14 @@
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(const_string "fpload_u")
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(const_string "fpload")))
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(const_string "fp")
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(if_then_else
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(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
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(const_string "fpstore_ux")
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(const_string "fpstore"))
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(if_then_else
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(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
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(const_string "fpload_ux")
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(const_string "fpload"))
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(const_string "vecsimple")
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(const_string "mfjmpr")
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(const_string "mtjmpr")
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(const_string "*")
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(const_string "vecsimple")
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(const_string "mftgpr")
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(const_string "mffgpr")
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(const_string "mftgpr")
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(const_string "mffgpr")])
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(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4,4,4,4")])
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(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
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;; Generate all one-bits and clear left or right.
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;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
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@ -1,3 +1,8 @@
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2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/59054
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* gcc.target/powerpc/pr59054.c: New test.
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2013-11-12 Adam Butcher <adam@jessamine.co.uk>
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* g++.dg/cpp1y/lambda-generic.C: New test case.
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18
gcc/testsuite/gcc.target/powerpc/pr59054.c
Normal file
18
gcc/testsuite/gcc.target/powerpc/pr59054.c
Normal file
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@ -0,0 +1,18 @@
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/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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/* { dg-require-effective-target powerpc_vsx_ok } */
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/* { dg-options "-mcpu=power7 -O0 -m64" } */
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long foo (void) { return 0; }
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/* { dg-final { scan-assembler-not "xxlor" } } */
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/* { dg-final { scan-assembler-not "stfd" } } */
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/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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/* { dg-require-effective-target powerpc_vsx_ok } */
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/* { dg-options "-mcpu=power7 -O0 -m64" } */
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long foo (void) { return 0; }
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/* { dg-final { scan-assembler-not "xxlor" } } */
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/* { dg-final { scan-assembler-not "stfd" } } */
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