rs6000: Move rs6000_split_multireg_move to later in file
An upcoming change to rs6000_split_multireg_move requires it to be moved later in the file to fix a declaration issue. 2021-07-14 Peter Bergner <bergner@linux.ibm.com> gcc/ * config/rs6000/rs6000.c (rs6000_split_multireg_move): Move to later in the file.
This commit is contained in:
Peter Bergner
parent
bebd8e9da8
commit
7d914777fc
1 changed files with 375 additions and 376 deletions
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@ -16690,382 +16690,6 @@ rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
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emit_move_insn (orig_after, after);
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}
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/* Emit instructions to move SRC to DST. Called by splitters for
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multi-register moves. It will emit at most one instruction for
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each register that is accessed; that is, it won't emit li/lis pairs
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(or equivalent for 64-bit code). One of SRC or DST must be a hard
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register. */
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void
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rs6000_split_multireg_move (rtx dst, rtx src)
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{
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/* The register number of the first register being moved. */
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int reg;
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/* The mode that is to be moved. */
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machine_mode mode;
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/* The mode that the move is being done in, and its size. */
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machine_mode reg_mode;
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int reg_mode_size;
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/* The number of registers that will be moved. */
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int nregs;
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reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
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mode = GET_MODE (dst);
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nregs = hard_regno_nregs (reg, mode);
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/* If we have a vector quad register for MMA, and this is a load or store,
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see if we can use vector paired load/stores. */
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if (mode == XOmode && TARGET_MMA
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&& (MEM_P (dst) || MEM_P (src)))
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{
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reg_mode = OOmode;
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nregs /= 2;
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}
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/* If we have a vector pair/quad mode, split it into two/four separate
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vectors. */
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else if (mode == OOmode || mode == XOmode)
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reg_mode = V1TImode;
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else if (FP_REGNO_P (reg))
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reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
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(TARGET_HARD_FLOAT ? DFmode : SFmode);
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else if (ALTIVEC_REGNO_P (reg))
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reg_mode = V16QImode;
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else
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reg_mode = word_mode;
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reg_mode_size = GET_MODE_SIZE (reg_mode);
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gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
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/* TDmode residing in FP registers is special, since the ISA requires that
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the lower-numbered word of a register pair is always the most significant
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word, even in little-endian mode. This does not match the usual subreg
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semantics, so we cannnot use simplify_gen_subreg in those cases. Access
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the appropriate constituent registers "by hand" in little-endian mode.
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Note we do not need to check for destructive overlap here since TDmode
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can only reside in even/odd register pairs. */
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if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
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{
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rtx p_src, p_dst;
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int i;
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for (i = 0; i < nregs; i++)
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{
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if (REG_P (src) && FP_REGNO_P (REGNO (src)))
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p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
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else
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p_src = simplify_gen_subreg (reg_mode, src, mode,
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i * reg_mode_size);
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if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
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p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
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else
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p_dst = simplify_gen_subreg (reg_mode, dst, mode,
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i * reg_mode_size);
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emit_insn (gen_rtx_SET (p_dst, p_src));
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}
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return;
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}
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/* The __vector_pair and __vector_quad modes are multi-register
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modes, so if we have to load or store the registers, we have to be
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careful to properly swap them if we're in little endian mode
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below. This means the last register gets the first memory
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location. We also need to be careful of using the right register
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numbers if we are splitting XO to OO. */
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if (mode == OOmode || mode == XOmode)
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{
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nregs = hard_regno_nregs (reg, mode);
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int reg_mode_nregs = hard_regno_nregs (reg, reg_mode);
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if (MEM_P (dst))
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{
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unsigned offset = 0;
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unsigned size = GET_MODE_SIZE (reg_mode);
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/* If we are reading an accumulator register, we have to
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deprime it before we can access it. */
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if (TARGET_MMA
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&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
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emit_insn (gen_mma_xxmfacc (src, src));
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for (int i = 0; i < nregs; i += reg_mode_nregs)
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{
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unsigned subreg =
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(WORDS_BIG_ENDIAN) ? i : (nregs - reg_mode_nregs - i);
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rtx dst2 = adjust_address (dst, reg_mode, offset);
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rtx src2 = gen_rtx_REG (reg_mode, reg + subreg);
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offset += size;
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emit_insn (gen_rtx_SET (dst2, src2));
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}
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return;
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}
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if (MEM_P (src))
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{
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unsigned offset = 0;
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unsigned size = GET_MODE_SIZE (reg_mode);
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for (int i = 0; i < nregs; i += reg_mode_nregs)
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{
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unsigned subreg =
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(WORDS_BIG_ENDIAN) ? i : (nregs - reg_mode_nregs - i);
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rtx dst2 = gen_rtx_REG (reg_mode, reg + subreg);
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rtx src2 = adjust_address (src, reg_mode, offset);
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offset += size;
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emit_insn (gen_rtx_SET (dst2, src2));
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}
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/* If we are writing an accumulator register, we have to
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prime it after we've written it. */
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if (TARGET_MMA
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&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
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emit_insn (gen_mma_xxmtacc (dst, dst));
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return;
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}
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if (GET_CODE (src) == UNSPEC)
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{
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gcc_assert (XINT (src, 1) == UNSPEC_MMA_ASSEMBLE);
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gcc_assert (REG_P (dst));
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if (GET_MODE (src) == XOmode)
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gcc_assert (FP_REGNO_P (REGNO (dst)));
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if (GET_MODE (src) == OOmode)
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gcc_assert (VSX_REGNO_P (REGNO (dst)));
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reg_mode = GET_MODE (XVECEXP (src, 0, 0));
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int nvecs = XVECLEN (src, 0);
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for (int i = 0; i < nvecs; i++)
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{
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int index = WORDS_BIG_ENDIAN ? i : nvecs - 1 - i;
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rtx dst_i = gen_rtx_REG (reg_mode, reg + index);
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emit_insn (gen_rtx_SET (dst_i, XVECEXP (src, 0, i)));
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}
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/* We are writing an accumulator register, so we have to
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prime it after we've written it. */
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if (GET_MODE (src) == XOmode)
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emit_insn (gen_mma_xxmtacc (dst, dst));
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return;
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}
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/* Register -> register moves can use common code. */
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}
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if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
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{
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/* If we are reading an accumulator register, we have to
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deprime it before we can access it. */
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if (TARGET_MMA
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&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
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emit_insn (gen_mma_xxmfacc (src, src));
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/* Move register range backwards, if we might have destructive
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overlap. */
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int i;
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/* XO/OO are opaque so cannot use subregs. */
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if (mode == OOmode || mode == XOmode )
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{
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for (i = nregs - 1; i >= 0; i--)
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{
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rtx dst_i = gen_rtx_REG (reg_mode, REGNO (dst) + i);
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rtx src_i = gen_rtx_REG (reg_mode, REGNO (src) + i);
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emit_insn (gen_rtx_SET (dst_i, src_i));
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}
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}
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else
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{
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for (i = nregs - 1; i >= 0; i--)
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emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
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i * reg_mode_size),
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simplify_gen_subreg (reg_mode, src, mode,
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i * reg_mode_size)));
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}
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/* If we are writing an accumulator register, we have to
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prime it after we've written it. */
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if (TARGET_MMA
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&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
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emit_insn (gen_mma_xxmtacc (dst, dst));
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}
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else
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{
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int i;
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int j = -1;
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bool used_update = false;
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rtx restore_basereg = NULL_RTX;
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if (MEM_P (src) && INT_REGNO_P (reg))
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{
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rtx breg;
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if (GET_CODE (XEXP (src, 0)) == PRE_INC
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|| GET_CODE (XEXP (src, 0)) == PRE_DEC)
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{
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rtx delta_rtx;
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breg = XEXP (XEXP (src, 0), 0);
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delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
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? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
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: GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
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emit_insn (gen_add3_insn (breg, breg, delta_rtx));
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src = replace_equiv_address (src, breg);
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}
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else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
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{
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if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
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{
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rtx basereg = XEXP (XEXP (src, 0), 0);
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if (TARGET_UPDATE)
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{
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rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
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emit_insn (gen_rtx_SET (ndst,
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gen_rtx_MEM (reg_mode,
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XEXP (src, 0))));
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used_update = true;
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}
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else
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emit_insn (gen_rtx_SET (basereg,
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XEXP (XEXP (src, 0), 1)));
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src = replace_equiv_address (src, basereg);
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}
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else
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{
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rtx basereg = gen_rtx_REG (Pmode, reg);
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emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
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src = replace_equiv_address (src, basereg);
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}
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}
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breg = XEXP (src, 0);
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if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
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breg = XEXP (breg, 0);
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/* If the base register we are using to address memory is
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also a destination reg, then change that register last. */
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if (REG_P (breg)
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&& REGNO (breg) >= REGNO (dst)
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&& REGNO (breg) < REGNO (dst) + nregs)
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j = REGNO (breg) - REGNO (dst);
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}
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else if (MEM_P (dst) && INT_REGNO_P (reg))
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{
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rtx breg;
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if (GET_CODE (XEXP (dst, 0)) == PRE_INC
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|| GET_CODE (XEXP (dst, 0)) == PRE_DEC)
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{
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rtx delta_rtx;
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breg = XEXP (XEXP (dst, 0), 0);
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delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
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? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
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: GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
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/* We have to update the breg before doing the store.
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Use store with update, if available. */
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if (TARGET_UPDATE)
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{
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rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
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emit_insn (TARGET_32BIT
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? (TARGET_POWERPC64
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? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
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: gen_movsi_si_update (breg, breg, delta_rtx, nsrc))
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: gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
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used_update = true;
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}
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else
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emit_insn (gen_add3_insn (breg, breg, delta_rtx));
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dst = replace_equiv_address (dst, breg);
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}
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else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
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&& GET_CODE (XEXP (dst, 0)) != LO_SUM)
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{
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if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
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{
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rtx basereg = XEXP (XEXP (dst, 0), 0);
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if (TARGET_UPDATE)
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{
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rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
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emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
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XEXP (dst, 0)),
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nsrc));
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used_update = true;
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}
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else
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emit_insn (gen_rtx_SET (basereg,
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XEXP (XEXP (dst, 0), 1)));
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dst = replace_equiv_address (dst, basereg);
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}
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else
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{
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rtx basereg = XEXP (XEXP (dst, 0), 0);
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rtx offsetreg = XEXP (XEXP (dst, 0), 1);
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gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
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&& REG_P (basereg)
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&& REG_P (offsetreg)
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&& REGNO (basereg) != REGNO (offsetreg));
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if (REGNO (basereg) == 0)
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{
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rtx tmp = offsetreg;
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offsetreg = basereg;
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basereg = tmp;
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}
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emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
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restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
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dst = replace_equiv_address (dst, basereg);
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}
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}
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else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
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gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
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}
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/* If we are reading an accumulator register, we have to
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deprime it before we can access it. */
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if (TARGET_MMA && REG_P (src)
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&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
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emit_insn (gen_mma_xxmfacc (src, src));
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for (i = 0; i < nregs; i++)
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{
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/* Calculate index to next subword. */
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++j;
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if (j == nregs)
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j = 0;
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/* If compiler already emitted move of first word by
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store with update, no need to do anything. */
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if (j == 0 && used_update)
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continue;
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/* XO/OO are opaque so cannot use subregs. */
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if (mode == OOmode || mode == XOmode )
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{
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rtx dst_i = gen_rtx_REG (reg_mode, REGNO (dst) + j);
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rtx src_i = gen_rtx_REG (reg_mode, REGNO (src) + j);
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emit_insn (gen_rtx_SET (dst_i, src_i));
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}
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else
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emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
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j * reg_mode_size),
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simplify_gen_subreg (reg_mode, src, mode,
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j * reg_mode_size)));
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}
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/* If we are writing an accumulator register, we have to
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prime it after we've written it. */
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if (TARGET_MMA && REG_P (dst)
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&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
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emit_insn (gen_mma_xxmtacc (dst, dst));
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if (restore_basereg != NULL_RTX)
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emit_insn (restore_basereg);
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}
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}
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static GTY(()) alias_set_type TOC_alias_set = -1;
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alias_set_type
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@ -26982,6 +26606,381 @@ rs6000_split_logical (rtx operands[3],
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return;
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}
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/* Emit instructions to move SRC to DST. Called by splitters for
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multi-register moves. It will emit at most one instruction for
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each register that is accessed; that is, it won't emit li/lis pairs
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(or equivalent for 64-bit code). One of SRC or DST must be a hard
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register. */
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void
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rs6000_split_multireg_move (rtx dst, rtx src)
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{
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/* The register number of the first register being moved. */
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int reg;
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/* The mode that is to be moved. */
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machine_mode mode;
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/* The mode that the move is being done in, and its size. */
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machine_mode reg_mode;
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int reg_mode_size;
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/* The number of registers that will be moved. */
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int nregs;
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reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
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mode = GET_MODE (dst);
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nregs = hard_regno_nregs (reg, mode);
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/* If we have a vector quad register for MMA, and this is a load or store,
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see if we can use vector paired load/stores. */
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if (mode == XOmode && TARGET_MMA
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&& (MEM_P (dst) || MEM_P (src)))
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{
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reg_mode = OOmode;
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nregs /= 2;
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}
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/* If we have a vector pair/quad mode, split it into two/four separate
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vectors. */
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else if (mode == OOmode || mode == XOmode)
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reg_mode = V1TImode;
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else if (FP_REGNO_P (reg))
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reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
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(TARGET_HARD_FLOAT ? DFmode : SFmode);
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else if (ALTIVEC_REGNO_P (reg))
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reg_mode = V16QImode;
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else
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reg_mode = word_mode;
|
||||
reg_mode_size = GET_MODE_SIZE (reg_mode);
|
||||
|
||||
gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
|
||||
|
||||
/* TDmode residing in FP registers is special, since the ISA requires that
|
||||
the lower-numbered word of a register pair is always the most significant
|
||||
word, even in little-endian mode. This does not match the usual subreg
|
||||
semantics, so we cannnot use simplify_gen_subreg in those cases. Access
|
||||
the appropriate constituent registers "by hand" in little-endian mode.
|
||||
|
||||
Note we do not need to check for destructive overlap here since TDmode
|
||||
can only reside in even/odd register pairs. */
|
||||
if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
|
||||
{
|
||||
rtx p_src, p_dst;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nregs; i++)
|
||||
{
|
||||
if (REG_P (src) && FP_REGNO_P (REGNO (src)))
|
||||
p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
|
||||
else
|
||||
p_src = simplify_gen_subreg (reg_mode, src, mode,
|
||||
i * reg_mode_size);
|
||||
|
||||
if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
|
||||
p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
|
||||
else
|
||||
p_dst = simplify_gen_subreg (reg_mode, dst, mode,
|
||||
i * reg_mode_size);
|
||||
|
||||
emit_insn (gen_rtx_SET (p_dst, p_src));
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* The __vector_pair and __vector_quad modes are multi-register
|
||||
modes, so if we have to load or store the registers, we have to be
|
||||
careful to properly swap them if we're in little endian mode
|
||||
below. This means the last register gets the first memory
|
||||
location. We also need to be careful of using the right register
|
||||
numbers if we are splitting XO to OO. */
|
||||
if (mode == OOmode || mode == XOmode)
|
||||
{
|
||||
nregs = hard_regno_nregs (reg, mode);
|
||||
int reg_mode_nregs = hard_regno_nregs (reg, reg_mode);
|
||||
if (MEM_P (dst))
|
||||
{
|
||||
unsigned offset = 0;
|
||||
unsigned size = GET_MODE_SIZE (reg_mode);
|
||||
|
||||
/* If we are reading an accumulator register, we have to
|
||||
deprime it before we can access it. */
|
||||
if (TARGET_MMA
|
||||
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
|
||||
emit_insn (gen_mma_xxmfacc (src, src));
|
||||
|
||||
for (int i = 0; i < nregs; i += reg_mode_nregs)
|
||||
{
|
||||
unsigned subreg =
|
||||
(WORDS_BIG_ENDIAN) ? i : (nregs - reg_mode_nregs - i);
|
||||
rtx dst2 = adjust_address (dst, reg_mode, offset);
|
||||
rtx src2 = gen_rtx_REG (reg_mode, reg + subreg);
|
||||
offset += size;
|
||||
emit_insn (gen_rtx_SET (dst2, src2));
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
if (MEM_P (src))
|
||||
{
|
||||
unsigned offset = 0;
|
||||
unsigned size = GET_MODE_SIZE (reg_mode);
|
||||
|
||||
for (int i = 0; i < nregs; i += reg_mode_nregs)
|
||||
{
|
||||
unsigned subreg =
|
||||
(WORDS_BIG_ENDIAN) ? i : (nregs - reg_mode_nregs - i);
|
||||
rtx dst2 = gen_rtx_REG (reg_mode, reg + subreg);
|
||||
rtx src2 = adjust_address (src, reg_mode, offset);
|
||||
offset += size;
|
||||
emit_insn (gen_rtx_SET (dst2, src2));
|
||||
}
|
||||
|
||||
/* If we are writing an accumulator register, we have to
|
||||
prime it after we've written it. */
|
||||
if (TARGET_MMA
|
||||
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
|
||||
emit_insn (gen_mma_xxmtacc (dst, dst));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
if (GET_CODE (src) == UNSPEC)
|
||||
{
|
||||
gcc_assert (XINT (src, 1) == UNSPEC_MMA_ASSEMBLE);
|
||||
gcc_assert (REG_P (dst));
|
||||
if (GET_MODE (src) == XOmode)
|
||||
gcc_assert (FP_REGNO_P (REGNO (dst)));
|
||||
if (GET_MODE (src) == OOmode)
|
||||
gcc_assert (VSX_REGNO_P (REGNO (dst)));
|
||||
|
||||
reg_mode = GET_MODE (XVECEXP (src, 0, 0));
|
||||
int nvecs = XVECLEN (src, 0);
|
||||
for (int i = 0; i < nvecs; i++)
|
||||
{
|
||||
int index = WORDS_BIG_ENDIAN ? i : nvecs - 1 - i;
|
||||
rtx dst_i = gen_rtx_REG (reg_mode, reg + index);
|
||||
emit_insn (gen_rtx_SET (dst_i, XVECEXP (src, 0, i)));
|
||||
}
|
||||
|
||||
/* We are writing an accumulator register, so we have to
|
||||
prime it after we've written it. */
|
||||
if (GET_MODE (src) == XOmode)
|
||||
emit_insn (gen_mma_xxmtacc (dst, dst));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* Register -> register moves can use common code. */
|
||||
}
|
||||
|
||||
if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
|
||||
{
|
||||
/* If we are reading an accumulator register, we have to
|
||||
deprime it before we can access it. */
|
||||
if (TARGET_MMA
|
||||
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
|
||||
emit_insn (gen_mma_xxmfacc (src, src));
|
||||
|
||||
/* Move register range backwards, if we might have destructive
|
||||
overlap. */
|
||||
int i;
|
||||
/* XO/OO are opaque so cannot use subregs. */
|
||||
if (mode == OOmode || mode == XOmode )
|
||||
{
|
||||
for (i = nregs - 1; i >= 0; i--)
|
||||
{
|
||||
rtx dst_i = gen_rtx_REG (reg_mode, REGNO (dst) + i);
|
||||
rtx src_i = gen_rtx_REG (reg_mode, REGNO (src) + i);
|
||||
emit_insn (gen_rtx_SET (dst_i, src_i));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for (i = nregs - 1; i >= 0; i--)
|
||||
emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
|
||||
i * reg_mode_size),
|
||||
simplify_gen_subreg (reg_mode, src, mode,
|
||||
i * reg_mode_size)));
|
||||
}
|
||||
|
||||
/* If we are writing an accumulator register, we have to
|
||||
prime it after we've written it. */
|
||||
if (TARGET_MMA
|
||||
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
|
||||
emit_insn (gen_mma_xxmtacc (dst, dst));
|
||||
}
|
||||
else
|
||||
{
|
||||
int i;
|
||||
int j = -1;
|
||||
bool used_update = false;
|
||||
rtx restore_basereg = NULL_RTX;
|
||||
|
||||
if (MEM_P (src) && INT_REGNO_P (reg))
|
||||
{
|
||||
rtx breg;
|
||||
|
||||
if (GET_CODE (XEXP (src, 0)) == PRE_INC
|
||||
|| GET_CODE (XEXP (src, 0)) == PRE_DEC)
|
||||
{
|
||||
rtx delta_rtx;
|
||||
breg = XEXP (XEXP (src, 0), 0);
|
||||
delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
|
||||
? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
|
||||
: GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
|
||||
emit_insn (gen_add3_insn (breg, breg, delta_rtx));
|
||||
src = replace_equiv_address (src, breg);
|
||||
}
|
||||
else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
|
||||
{
|
||||
if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
|
||||
{
|
||||
rtx basereg = XEXP (XEXP (src, 0), 0);
|
||||
if (TARGET_UPDATE)
|
||||
{
|
||||
rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
|
||||
emit_insn (gen_rtx_SET (ndst,
|
||||
gen_rtx_MEM (reg_mode,
|
||||
XEXP (src, 0))));
|
||||
used_update = true;
|
||||
}
|
||||
else
|
||||
emit_insn (gen_rtx_SET (basereg,
|
||||
XEXP (XEXP (src, 0), 1)));
|
||||
src = replace_equiv_address (src, basereg);
|
||||
}
|
||||
else
|
||||
{
|
||||
rtx basereg = gen_rtx_REG (Pmode, reg);
|
||||
emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
|
||||
src = replace_equiv_address (src, basereg);
|
||||
}
|
||||
}
|
||||
|
||||
breg = XEXP (src, 0);
|
||||
if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
|
||||
breg = XEXP (breg, 0);
|
||||
|
||||
/* If the base register we are using to address memory is
|
||||
also a destination reg, then change that register last. */
|
||||
if (REG_P (breg)
|
||||
&& REGNO (breg) >= REGNO (dst)
|
||||
&& REGNO (breg) < REGNO (dst) + nregs)
|
||||
j = REGNO (breg) - REGNO (dst);
|
||||
}
|
||||
else if (MEM_P (dst) && INT_REGNO_P (reg))
|
||||
{
|
||||
rtx breg;
|
||||
|
||||
if (GET_CODE (XEXP (dst, 0)) == PRE_INC
|
||||
|| GET_CODE (XEXP (dst, 0)) == PRE_DEC)
|
||||
{
|
||||
rtx delta_rtx;
|
||||
breg = XEXP (XEXP (dst, 0), 0);
|
||||
delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
|
||||
? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
|
||||
: GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
|
||||
|
||||
/* We have to update the breg before doing the store.
|
||||
Use store with update, if available. */
|
||||
|
||||
if (TARGET_UPDATE)
|
||||
{
|
||||
rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
|
||||
emit_insn (TARGET_32BIT
|
||||
? (TARGET_POWERPC64
|
||||
? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
|
||||
: gen_movsi_si_update (breg, breg, delta_rtx, nsrc))
|
||||
: gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
|
||||
used_update = true;
|
||||
}
|
||||
else
|
||||
emit_insn (gen_add3_insn (breg, breg, delta_rtx));
|
||||
dst = replace_equiv_address (dst, breg);
|
||||
}
|
||||
else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
|
||||
&& GET_CODE (XEXP (dst, 0)) != LO_SUM)
|
||||
{
|
||||
if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
|
||||
{
|
||||
rtx basereg = XEXP (XEXP (dst, 0), 0);
|
||||
if (TARGET_UPDATE)
|
||||
{
|
||||
rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
|
||||
emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
|
||||
XEXP (dst, 0)),
|
||||
nsrc));
|
||||
used_update = true;
|
||||
}
|
||||
else
|
||||
emit_insn (gen_rtx_SET (basereg,
|
||||
XEXP (XEXP (dst, 0), 1)));
|
||||
dst = replace_equiv_address (dst, basereg);
|
||||
}
|
||||
else
|
||||
{
|
||||
rtx basereg = XEXP (XEXP (dst, 0), 0);
|
||||
rtx offsetreg = XEXP (XEXP (dst, 0), 1);
|
||||
gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
|
||||
&& REG_P (basereg)
|
||||
&& REG_P (offsetreg)
|
||||
&& REGNO (basereg) != REGNO (offsetreg));
|
||||
if (REGNO (basereg) == 0)
|
||||
{
|
||||
rtx tmp = offsetreg;
|
||||
offsetreg = basereg;
|
||||
basereg = tmp;
|
||||
}
|
||||
emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
|
||||
restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
|
||||
dst = replace_equiv_address (dst, basereg);
|
||||
}
|
||||
}
|
||||
else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
|
||||
gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
|
||||
}
|
||||
|
||||
/* If we are reading an accumulator register, we have to
|
||||
deprime it before we can access it. */
|
||||
if (TARGET_MMA && REG_P (src)
|
||||
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
|
||||
emit_insn (gen_mma_xxmfacc (src, src));
|
||||
|
||||
for (i = 0; i < nregs; i++)
|
||||
{
|
||||
/* Calculate index to next subword. */
|
||||
++j;
|
||||
if (j == nregs)
|
||||
j = 0;
|
||||
|
||||
/* If compiler already emitted move of first word by
|
||||
store with update, no need to do anything. */
|
||||
if (j == 0 && used_update)
|
||||
continue;
|
||||
|
||||
/* XO/OO are opaque so cannot use subregs. */
|
||||
if (mode == OOmode || mode == XOmode )
|
||||
{
|
||||
rtx dst_i = gen_rtx_REG (reg_mode, REGNO (dst) + j);
|
||||
rtx src_i = gen_rtx_REG (reg_mode, REGNO (src) + j);
|
||||
emit_insn (gen_rtx_SET (dst_i, src_i));
|
||||
}
|
||||
else
|
||||
emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
|
||||
j * reg_mode_size),
|
||||
simplify_gen_subreg (reg_mode, src, mode,
|
||||
j * reg_mode_size)));
|
||||
}
|
||||
|
||||
/* If we are writing an accumulator register, we have to
|
||||
prime it after we've written it. */
|
||||
if (TARGET_MMA && REG_P (dst)
|
||||
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
|
||||
emit_insn (gen_mma_xxmtacc (dst, dst));
|
||||
|
||||
if (restore_basereg != NULL_RTX)
|
||||
emit_insn (restore_basereg);
|
||||
}
|
||||
}
|
||||
|
||||
/* Return true if the peephole2 can combine a load involving a combination of
|
||||
an addis instruction and a load with an offset that can be fused together on
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue