i386.md (popdi1): Rewrite using POST_INC memory operand.
* config/i386/i386.md (popdi1): Rewrite using POST_INC memory operand.
(popsi1): Ditto.
(*popdi1_epilogue): Ditto.
(*popsi1_epilogue): Ditto.
(popsi, popdi peephole2 patterns): Update peepholes for changed
pop{si,di}1 and *pop{si,di}1_epilogue patterns.
(pop<mode>1): Macroize insn from pop{si,di}1 using P code iterator.
(*pop<mode>1_epilogue): Ditto from *pop{si,di}1_epilogue.
* config/i386/i386.c (*ix86_gen_pop1): Remove indirect function.
(override_options): Do not initialize removed ix86_gen_pop1.
(gen_pop): New static function.
(ix86_expand_prologue): Use gen_pop instead of ix86_gen_pop1.
(release_scratch_register_on_entry): Ditto.
(ix86_restore_reg_using_pop): Ditto.
(ix86_expand_epilogue): Ditto.
From-SVN: r163679
This commit is contained in:
Uros Bizjak
parent
0f643366ab
commit
7d2c38c0b9
3 changed files with 91 additions and 123 deletions
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@ -1,3 +1,23 @@
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2010-08-31 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (popdi1): Rewrite using POST_INC memory operand.
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(popsi1): Ditto.
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(*popdi1_epilogue): Ditto.
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(*popsi1_epilogue): Ditto.
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(popsi, popdi peephole2 patterns): Update peepholes for changed
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pop{si,di}1 and *pop{si,di}1_epilogue patterns.
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(pop<mode>1): Macroize insn from pop{si,di}1 using P code iterator.
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(*pop<mode>1_epilogue): Ditto from *pop{si,di}1_epilogue.
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* config/i386/i386.c (*ix86_gen_pop1): Remove indirect function.
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(override_options): Do not initialize removed ix86_gen_pop1.
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(gen_pop): New static function.
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(ix86_expand_prologue): Use gen_pop instead of ix86_gen_pop1.
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(release_scratch_register_on_entry): Ditto.
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(ix86_restore_reg_using_pop): Ditto.
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(ix86_expand_epilogue): Ditto.
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2010-08-31 Jakub Jelinek <jakub@redhat.com>
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PR middle-end/45461
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@ -414,9 +434,9 @@
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(VSr3): Ditto.
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2010-08-27 Basile Starynkevitch <basile@starynkevitch.net>
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Jeremie Salvucci <jeremie.salvucci@free.fr>
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Jeremie Salvucci <jeremie.salvucci@free.fr>
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* gengtype.c (output_type_enum): Test the right union member.
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* gengtype.c (output_type_enum): Test the right union member.
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2010-08-27 Uros Bizjak <ubizjak@gmail.com>
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@ -1896,7 +1896,6 @@ static const char ix86_force_align_arg_pointer_string[]
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= "force_align_arg_pointer";
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static rtx (*ix86_gen_leave) (void);
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static rtx (*ix86_gen_pop1) (rtx);
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static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
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static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
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static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx, rtx);
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@ -3655,7 +3654,6 @@ override_options (bool main_args_p)
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if (TARGET_64BIT)
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{
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ix86_gen_leave = gen_leave_rex64;
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ix86_gen_pop1 = gen_popdi1;
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ix86_gen_add3 = gen_adddi3;
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ix86_gen_sub3 = gen_subdi3;
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ix86_gen_sub3_carry = gen_subdi3_carry;
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@ -3669,7 +3667,6 @@ override_options (bool main_args_p)
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else
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{
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ix86_gen_leave = gen_leave;
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ix86_gen_pop1 = gen_popsi1;
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ix86_gen_add3 = gen_addsi3;
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ix86_gen_sub3 = gen_subsi3;
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ix86_gen_sub3_carry = gen_subsi3_carry;
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@ -8173,6 +8170,18 @@ gen_push (rtx arg)
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arg);
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}
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/* Generate an "pop" pattern for input ARG. */
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static rtx
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gen_pop (rtx arg)
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{
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return gen_rtx_SET (VOIDmode,
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arg,
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gen_rtx_MEM (Pmode,
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gen_rtx_POST_INC (Pmode,
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stack_pointer_rtx)));
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}
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/* Return >= 0 if there is an unused call-clobbered register available
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for the entire function. */
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@ -9052,7 +9061,7 @@ release_scratch_register_on_entry (struct scratch_reg *sr)
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{
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if (sr->saved)
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{
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rtx x, insn = emit_insn (ix86_gen_pop1 (sr->reg));
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rtx x, insn = emit_insn (gen_pop (sr->reg));
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/* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
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RTX_FRAME_RELATED_P (insn) = 1;
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@ -9478,7 +9487,7 @@ ix86_expand_prologue (void)
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{
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/* The frame pointer is not needed so pop %ebp again.
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This leaves us with a pristine state. */
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emit_insn (ix86_gen_pop1 (hard_frame_pointer_rtx));
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emit_insn (gen_pop (hard_frame_pointer_rtx));
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}
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}
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@ -9786,7 +9795,7 @@ static void
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ix86_emit_restore_reg_using_pop (rtx reg)
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{
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struct machine_function *m = cfun->machine;
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rtx insn = emit_insn (ix86_gen_pop1 (reg));
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rtx insn = emit_insn (gen_pop (reg));
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ix86_add_cfa_restore_note (insn, reg, m->fs.sp_offset);
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m->fs.sp_offset -= UNITS_PER_WORD;
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@ -9809,10 +9818,12 @@ ix86_emit_restore_reg_using_pop (rtx reg)
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if (m->fs.cfa_reg == stack_pointer_rtx)
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{
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m->fs.cfa_offset -= UNITS_PER_WORD;
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add_reg_note (insn, REG_CFA_ADJUST_CFA,
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copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
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rtx x = plus_constant (stack_pointer_rtx, UNITS_PER_WORD);
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x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
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add_reg_note (insn, REG_CFA_ADJUST_CFA, x);
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RTX_FRAME_RELATED_P (insn) = 1;
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m->fs.cfa_offset -= UNITS_PER_WORD;
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}
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/* When the frame pointer is the CFA, and we pop it, we are
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@ -10229,7 +10240,7 @@ ix86_expand_epilogue (int style)
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/* There is no "pascal" calling convention in any 64bit ABI. */
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gcc_assert (!TARGET_64BIT);
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insn = emit_insn (gen_popsi1 (ecx));
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insn = emit_insn (gen_pop (ecx));
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m->fs.cfa_offset -= UNITS_PER_WORD;
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m->fs.sp_offset -= UNITS_PER_WORD;
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@ -1636,14 +1636,7 @@
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""
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"ix86_expand_move (<MODE>mode, operands); DONE;")
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;; Push/pop instructions. They are separate since autoinc/dec is not a
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;; general_operand.
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;;
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;; %%% We don't use a post-inc memory reference because x86 is not a
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;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
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;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
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;; targets without our curiosities, and it is just as easy to represent
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;; this differently.
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;; Push/pop instructions.
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(define_insn "*pushdi2_rex64"
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[(set (match_operand:DI 0 "push_operand" "=<,!<")
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@ -1756,47 +1749,22 @@
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[(set_attr "type" "push")
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(set_attr "mode" "<MODE>")])
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(define_insn "popdi1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
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(mem:DI (reg:DI SP_REG)))
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(set (reg:DI SP_REG)
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(plus:DI (reg:DI SP_REG) (const_int 8)))]
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"TARGET_64BIT"
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"pop{q}\t%0"
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(define_insn "pop<mode>1"
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[(set (match_operand:P 0 "nonimmediate_operand" "=r*m")
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(match_operand:P 1 "pop_operand" ">"))]
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""
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"pop{<imodesuffix>}\t%0"
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[(set_attr "type" "pop")
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(set_attr "mode" "DI")])
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(set_attr "mode" "<MODE>")])
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(define_insn "popsi1"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
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(mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG) (const_int 4)))]
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"!TARGET_64BIT"
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"pop{l}\t%0"
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[(set_attr "type" "pop")
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(set_attr "mode" "SI")])
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(define_insn "*popdi1_epilogue"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
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(mem:DI (reg:DI SP_REG)))
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(set (reg:DI SP_REG)
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(plus:DI (reg:DI SP_REG) (const_int 8)))
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(define_insn "*pop<mode>1_epilogue"
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[(set (match_operand:P 0 "nonimmediate_operand" "=r*m")
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(match_operand:P 1 "pop_operand" ">"))
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(clobber (mem:BLK (scratch)))]
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"TARGET_64BIT"
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"pop{q}\t%0"
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""
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"pop{<imodesuffix>}\t%0"
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[(set_attr "type" "pop")
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(set_attr "mode" "DI")])
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(define_insn "*popsi1_epilogue"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
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(mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG) (const_int 4)))
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(clobber (mem:BLK (scratch)))]
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"!TARGET_64BIT"
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"pop{l}\t%0"
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[(set_attr "type" "pop")
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(set_attr "mode" "SI")])
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(set_attr "mode" "<MODE>")])
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(define_insn "*mov<mode>_xor"
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[(set (match_operand:SWI48 0 "register_operand" "=r")
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@ -17037,12 +17005,13 @@
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"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
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;; The ESP adjustments can be done by the push and pop instructions. Resulting
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;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
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;; many CPUs it is also faster, since special hardware to avoid esp
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;; code is shorter, since push is only 1 byte, while add imm, %esp is 3 bytes.
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;; On many CPUs it is also faster, since special hardware to avoid esp
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;; dependencies is present.
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;; While some of these conversions may be done using splitters, we use peepholes
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;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
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;; While some of these conversions may be done using splitters, we use
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;; peepholes in order to allow combine_stack_adjustments pass to see
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;; nonobfuscated RTL.
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;; Convert prologue esp subtractions to push.
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;; We need register to push. In order to keep verify_flow_info happy we have
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@ -17101,13 +17070,11 @@
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(clobber (reg:CC FLAGS_REG))
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(clobber (mem:BLK (scratch)))])]
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"optimize_insn_for_size_p () || !TARGET_ADD_ESP_4"
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[(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
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(clobber (mem:BLK (scratch)))])]
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"")
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[(parallel [(set (match_dup 0) (mem:SI (post_inc:SI (reg:SI SP_REG))))
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(clobber (mem:BLK (scratch)))])])
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;; Two pops case is tricky, since pop causes dependency on destination register.
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;; We use two registers if available.
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;; Two pops case is tricky, since pop causes dependency
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;; on destination register. We use two registers if available.
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(define_peephole2
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[(match_scratch:SI 0 "r")
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(match_scratch:SI 1 "r")
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@ -17115,12 +17082,9 @@
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(clobber (reg:CC FLAGS_REG))
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(clobber (mem:BLK (scratch)))])]
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"optimize_insn_for_size_p () || !TARGET_ADD_ESP_8"
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[(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
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[(parallel [(set (match_dup 0) (mem:SI (post_inc:SI (reg:SI SP_REG))))
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(clobber (mem:BLK (scratch)))])
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(parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
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"")
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(set (match_dup 1) (mem:SI (post_inc:SI (reg:SI SP_REG))))])
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(define_peephole2
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[(match_scratch:SI 0 "r")
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@ -17128,12 +17092,9 @@
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(clobber (reg:CC FLAGS_REG))
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(clobber (mem:BLK (scratch)))])]
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"optimize_insn_for_size_p ()"
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[(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
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[(parallel [(set (match_dup 0) (mem:SI (post_inc:SI (reg:SI SP_REG))))
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(clobber (mem:BLK (scratch)))])
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(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
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"")
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(set (match_dup 0) (mem:SI (post_inc:SI (reg:SI SP_REG))))])
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;; Convert esp additions to pop.
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(define_peephole2
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@ -17141,34 +17102,26 @@
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(parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
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(clobber (reg:CC FLAGS_REG))])]
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""
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[(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
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"")
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[(set (match_dup 0) (mem:SI (post_inc:SI (reg:SI SP_REG))))])
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;; Two pops case is tricky, since pop causes dependency on destination register.
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;; We use two registers if available.
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;; Two pops case is tricky, since pop causes dependency
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;; on destination register. We use two registers if available.
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(define_peephole2
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[(match_scratch:SI 0 "r")
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(match_scratch:SI 1 "r")
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(parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
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(clobber (reg:CC FLAGS_REG))])]
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""
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[(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
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(parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
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"")
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[(set (match_dup 0) (mem:SI (post_inc:SI (reg:SI SP_REG))))
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(set (match_dup 1) (mem:SI (post_inc:SI (reg:SI SP_REG))))])
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(define_peephole2
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[(match_scratch:SI 0 "r")
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(parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
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(clobber (reg:CC FLAGS_REG))])]
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"optimize_insn_for_size_p ()"
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[(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
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(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
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"")
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[(set (match_dup 0) (mem:SI (post_inc:SI (reg:SI SP_REG))))
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(set (match_dup 0) (mem:SI (post_inc:SI (reg:SI SP_REG))))])
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(define_peephole2
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[(match_scratch:DI 0 "r")
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@ -17216,13 +17169,11 @@
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(clobber (reg:CC FLAGS_REG))
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(clobber (mem:BLK (scratch)))])]
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"optimize_insn_for_size_p () || !TARGET_ADD_ESP_4"
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[(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
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(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
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(clobber (mem:BLK (scratch)))])]
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"")
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[(parallel [(set (match_dup 0) (mem:DI (post_inc:DI (reg:DI SP_REG))))
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(clobber (mem:BLK (scratch)))])])
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|
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;; Two pops case is tricky, since pop causes dependency on destination register.
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;; We use two registers if available.
|
||||
;; Two pops case is tricky, since pop causes dependency
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;; on destination register. We use two registers if available.
|
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(define_peephole2
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[(match_scratch:DI 0 "r")
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(match_scratch:DI 1 "r")
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|
|
@ -17230,12 +17181,9 @@
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(clobber (reg:CC FLAGS_REG))
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(clobber (mem:BLK (scratch)))])]
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"optimize_insn_for_size_p () || !TARGET_ADD_ESP_8"
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[(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
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(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
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[(parallel [(set (match_dup 0) (mem:DI (post_inc:DI (reg:DI SP_REG))))
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(clobber (mem:BLK (scratch)))])
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(parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
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(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
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"")
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(set (match_dup 1) (mem:DI (post_inc:DI (reg:DI SP_REG))))])
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|
||||
(define_peephole2
|
||||
[(match_scratch:DI 0 "r")
|
||||
|
|
@ -17243,12 +17191,9 @@
|
|||
(clobber (reg:CC FLAGS_REG))
|
||||
(clobber (mem:BLK (scratch)))])]
|
||||
"optimize_insn_for_size_p ()"
|
||||
[(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
|
||||
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
|
||||
[(parallel [(set (match_dup 0) (mem:DI (post_inc:DI (reg:DI SP_REG))))
|
||||
(clobber (mem:BLK (scratch)))])
|
||||
(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
|
||||
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
|
||||
"")
|
||||
(set (match_dup 0) (mem:DI (post_inc:DI (reg:DI SP_REG))))])
|
||||
|
||||
;; Convert esp additions to pop.
|
||||
(define_peephole2
|
||||
|
|
@ -17256,34 +17201,26 @@
|
|||
(parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
""
|
||||
[(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
|
||||
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
|
||||
"")
|
||||
[(set (match_dup 0) (mem:DI (post_inc:DI (reg:DI SP_REG))))])
|
||||
|
||||
;; Two pops case is tricky, since pop causes dependency on destination register.
|
||||
;; We use two registers if available.
|
||||
;; Two pops case is tricky, since pop causes dependency
|
||||
;; on destination register. We use two registers if available.
|
||||
(define_peephole2
|
||||
[(match_scratch:DI 0 "r")
|
||||
(match_scratch:DI 1 "r")
|
||||
(parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
""
|
||||
[(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
|
||||
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
|
||||
(parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
|
||||
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
|
||||
"")
|
||||
[(set (match_dup 0) (mem:DI (post_inc:DI (reg:DI SP_REG))))
|
||||
(set (match_dup 1) (mem:DI (post_inc:DI (reg:DI SP_REG))))])
|
||||
|
||||
(define_peephole2
|
||||
[(match_scratch:DI 0 "r")
|
||||
(parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"optimize_insn_for_size_p ()"
|
||||
[(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
|
||||
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
|
||||
(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
|
||||
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
|
||||
"")
|
||||
[(set (match_dup 0) (mem:DI (post_inc:DI (reg:DI SP_REG))))
|
||||
(set (match_dup 0) (mem:DI (post_inc:DI (reg:DI SP_REG))))])
|
||||
|
||||
;; Convert compares with 1 to shorter inc/dec operations when CF is not
|
||||
;; required and register dies. Similarly for 128 to -128.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue