From 7cd5235bad7e352c5364dcdac82bf123d42aa154 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Tue, 1 Jul 1997 15:08:07 +0000 Subject: [PATCH] fix previous change From-SVN: r14364 --- gcc/config/rs6000/rs6000.md | 214 +++++++++++++++++++----------------- 1 file changed, 112 insertions(+), 102 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 0e6e259c8c8..87106736d94 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -858,20 +858,44 @@ ;; Discourage ai/addic because of carry but provide it in an alternative ;; allowing register zero as source. -(define_insn "addsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r,r") - (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b,b") - (match_operand:SI 2 "reg_or_cint_operand" "r,I,I,J,n")))] +(define_expand "addsi3" + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_cint_operand" "")))] + "" + " +{ + if (GET_CODE (operands[2]) == CONST_INT && !add_operand (operands[2], SImode)) + { + rtx tmp = ((reload_in_progress || reload_completed + || rtx_equal_p (operands[0], operands[1])) + ? operands[0] : gen_reg_rtx (SImode)); + + HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; + HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); + + if (low & 0x8000) + high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; + + emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high))); + emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); + DONE; + } +}") + +(define_insn "*addsi3_internal1" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") + (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") + (match_operand:SI 2 "add_operand" "r,I,I,J")))] "" "@ {cax|add} %0,%1,%2 {cal %0,%2(%1)|addi %0,%1,%2} {ai|addic} %0,%1,%2 - {cau|addis} %0,%1,%v2 - #" - [(set_attr "length" "4,4,4,4,8")]) + {cau|addis} %0,%1,%v2" + [(set_attr "length" "4,4,4,4")]) -(define_insn "" +(define_insn "*addsi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "reg_or_short_operand" "r,I")) @@ -883,7 +907,7 @@ {ai.|addic.} %3,%1,%2" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*addsi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "reg_or_short_operand" "r,I")) @@ -1648,20 +1672,19 @@ [(set_attr "type" "idiv")]) (define_insn "andsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") - (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "?r,L,K,J,n"))) - (clobber (match_scratch:CC 3 "=X,X,x,x,x"))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") + (match_operand:SI 2 "and_operand" "?r,L,K,J"))) + (clobber (match_scratch:CC 3 "=X,X,x,x"))] "" "@ and %0,%1,%2 {rlinm|rlwinm} %0,%1,0,%m2,%M2 {andil.|andi.} %0,%1,%b2 - {andiu.|andis.} %0,%1,%u2 - #" - [(set_attr "length" "4,4,4,4,8")]) + {andiu.|andis.} %0,%1,%u2" + [(set_attr "length" "4,4,4,4")]) -(define_insn "" +(define_insn "*andsi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") (match_operand:SI 2 "and_operand" "r,K,J,L")) @@ -1675,7 +1698,7 @@ {rlinm.|rlwinm.} %3,%1,0,%m2,%M2" [(set_attr "type" "compare,compare,compare,delayed_compare")]) -(define_insn "" +(define_insn "*andsi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") (match_operand:SI 2 "and_operand" "r,K,J,L")) @@ -1690,40 +1713,39 @@ {rlinm.|rlwinm.} %0,%1,0,%m2,%M2" [(set_attr "type" "compare,compare,compare,delayed_compare")]) -;; Take a AND with a constant that cannot be done in a single insn and try to -;; split it into two insns. - -(define_split +(define_expand "iorsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "non_and_cint_operand" ""))) - (clobber (match_scratch:CC 3 ""))] - "reload_completed" - [(parallel [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 4))) (clobber (match_dup 6))]) - (parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 5))) (clobber (match_dup 7))])] + (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_cint_operand" "")))] + "" " { - operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff0000); - operands[5] = GEN_INT (INTVAL (operands[2]) & 0x0000ffff); - operands[6] = ((mask_constant (INTVAL (operands[4]))) - ? gen_rtx (SCRATCH, CCmode) - : operands[3]); - operands[7] = operands[3]; + if (GET_CODE (operands[2]) == CONST_INT + && !logical_operand (operands[2], SImode)) + { + HOST_WIDE_INT value = INTVAL (operands[2]); + rtx tmp = ((reload_in_progress || reload_completed + || rtx_equal_p (operands[0], operands[1])) + ? operands[0] : gen_reg_rtx (SImode)); + + emit_insn (gen_iorsi3 (tmp, operands[1], GEN_INT (value & 0xffff0000))); + emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0x0000ffff))); + DONE; + } }") -(define_insn "iorsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,K,J,n")))] +(define_insn "*iorsi3_internal1" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") + (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") + (match_operand:SI 2 "logical_operand" "r,K,J")))] "" "@ or %0,%1,%2 {oril|ori} %0,%1,%b2 - {oriu|oris} %0,%1,%u2 - #" - [(set_attr "length" "4,4,4,8")]) + {oriu|oris} %0,%1,%u2" + [(set_attr "length" "4,4,4")]) -(define_insn "" +(define_insn "*iorsi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "gpc_reg_operand" "r")) @@ -1733,7 +1755,7 @@ "or. %3,%1,%2" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*iorsi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "gpc_reg_operand" "r")) @@ -1744,35 +1766,39 @@ "or. %0,%1,%2" [(set_attr "type" "compare")]) -;; Split an IOR that we can't do in one insn into two insns, each of which -;; does one 16-bit part. - -(define_split +(define_expand "xorsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "") - (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "non_logical_cint_operand" "")))] + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_cint_operand" "")))] "" - [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) - (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] -" + " { - operands[3] = GEN_INT (INTVAL (operands[2]) & 0xffff0000); - operands[4] = GEN_INT (INTVAL (operands[2]) & 0x0000ffff); + if (GET_CODE (operands[2]) == CONST_INT + && !logical_operand (operands[2], SImode)) + { + HOST_WIDE_INT value = INTVAL (operands[2]); + rtx tmp = ((reload_in_progress || reload_completed + || rtx_equal_p (operands[0], operands[1])) + ? operands[0] : gen_reg_rtx (SImode)); + + emit_insn (gen_xorsi3 (tmp, operands[1], GEN_INT (value & 0xffff0000))); + emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0x0000ffff))); + DONE; + } }") -(define_insn "xorsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,K,J,n")))] +(define_insn "*xorsi3_internal1" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") + (match_operand:SI 2 "logical_operand" "r,K,J")))] "" "@ xor %0,%1,%2 {xoril|xori} %0,%1,%b2 - {xoriu|xoris} %0,%1,%u2 - #" - [(set_attr "length" "4,4,4,8")]) + {xoriu|xoris} %0,%1,%u2" + [(set_attr "length" "4,4,4")]) -(define_insn "" +(define_insn "*xorsi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "gpc_reg_operand" "r")) @@ -1782,7 +1808,7 @@ "xor. %3,%1,%2" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*xorsi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "gpc_reg_operand" "r")) @@ -1793,30 +1819,14 @@ "xor. %0,%1,%2" [(set_attr "type" "compare")]) -;; Split an XOR that we can't do in one insn into two insns, each of which -;; does one 16-bit part. - -(define_split - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "non_logical_cint_operand" "")))] - "" - [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) - (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] -" -{ - operands[3] = GEN_INT (INTVAL (operands[2]) & 0xffff0000); - operands[4] = GEN_INT (INTVAL (operands[2]) & 0x0000ffff); -}") - -(define_insn "" +(define_insn "*eqv_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "eqv %0,%1,%2") -(define_insn "" +(define_insn "*eqv_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "gpc_reg_operand" "r"))) @@ -1826,7 +1836,7 @@ "eqv. %3,%1,%2" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*eqv_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "gpc_reg_operand" "r"))) @@ -1837,14 +1847,14 @@ "eqv. %0,%1,%2" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*andc_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r")))] "" "andc %0,%2,%1") -(define_insn "" +(define_insn "*andc_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r")) @@ -1854,7 +1864,7 @@ "andc. %3,%2,%1" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*andc_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r")) @@ -1865,14 +1875,14 @@ "andc. %0,%2,%1" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*iorc_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r")))] "" "orc %0,%2,%1") -(define_insn "" +(define_insn "*iorc_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r")) @@ -1882,7 +1892,7 @@ "orc. %3,%2,%1" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*iorc_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r")) @@ -1893,14 +1903,14 @@ "orc. %0,%2,%1" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*nand_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "nand %0,%1,%2") -(define_insn "" +(define_insn "*nand_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) @@ -1910,7 +1920,7 @@ "nand. %3,%1,%2" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*nand_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) @@ -1921,14 +1931,14 @@ "nand. %0,%1,%2" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*nor_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "nor %0,%1,%2") -(define_insn "" +(define_insn "*nor_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) @@ -1938,7 +1948,7 @@ "nor. %3,%1,%2" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*nor_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) @@ -1953,7 +1963,7 @@ ;; orders. Don't define forms that only set CR fields because these ;; would modify an input register. -(define_insn "" +(define_insn "*maskir_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 1 "gpc_reg_operand" "0")) @@ -1962,7 +1972,7 @@ "TARGET_POWER" "maskir %0,%3,%2") -(define_insn "" +(define_insn "*maskir_internal2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 1 "gpc_reg_operand" "0")) @@ -1971,7 +1981,7 @@ "TARGET_POWER" "maskir %0,%3,%2") -(define_insn "" +(define_insn "*maskir_internal3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") (match_operand:SI 3 "gpc_reg_operand" "r")) @@ -1980,7 +1990,7 @@ "TARGET_POWER" "maskir %0,%3,%2") -(define_insn "" +(define_insn "*maskir_internal4" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") (match_operand:SI 2 "gpc_reg_operand" "r")) @@ -1989,7 +1999,7 @@ "TARGET_POWER" "maskir %0,%3,%2") -(define_insn "" +(define_insn "*maskir_internal5" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) @@ -2004,7 +2014,7 @@ "maskir. %0,%3,%2" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*maskir_internal6" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) @@ -2019,7 +2029,7 @@ "maskir. %0,%3,%2" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*maskir_internal7" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") @@ -2034,7 +2044,7 @@ "maskir. %0,%3,%2" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*maskir_internal8" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")