RISC-V: Refine the rtl expand check for strided ld/st
This patch would like to remove the unnecessary option for the strided load/store testcases. After fix the option from the rvv.exp, both the O2 and O3 will be passed to the test files for rtl expand dump check but the O2 has 2 time for IFN while the O3 has 4 times with -fvectorize specificed. Thus, add xfail O2 for IFN 4 times check, as well as xfail O3 for 2 times check. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Remove unnecessary optimization option and xfail O2/O3 diff IFN times from the rtl expand dump. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
parent
c10767d0e4
commit
7c7da10365
11 changed files with 55 additions and 33 deletions
|
@ -1,11 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
|
||||
#include "strided_ld_st.h"
|
||||
|
||||
DEF_STRIDED_LD_ST_FORM_1(_Float16)
|
||||
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-assembler-times {vlse16.v} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsse16.v} 1 } } */
|
||||
|
|
|
@ -1,11 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
|
||||
#include "strided_ld_st.h"
|
||||
|
||||
DEF_STRIDED_LD_ST_FORM_1(float)
|
||||
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-assembler-times {vlse32.v} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsse32.v} 1 } } */
|
||||
|
|
|
@ -1,11 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
|
||||
#include "strided_ld_st.h"
|
||||
|
||||
DEF_STRIDED_LD_ST_FORM_1(double)
|
||||
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
|
||||
|
|
|
@ -1,11 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
|
||||
#include "strided_ld_st.h"
|
||||
|
||||
DEF_STRIDED_LD_ST_FORM_1(int16_t)
|
||||
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-assembler-times {vlse16.v} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsse16.v} 1 } } */
|
||||
|
|
|
@ -1,11 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
|
||||
#include "strided_ld_st.h"
|
||||
|
||||
DEF_STRIDED_LD_ST_FORM_1(int32_t)
|
||||
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-assembler-times {vlse32.v} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsse32.v} 1 } } */
|
||||
|
|
|
@ -1,11 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
|
||||
#include "strided_ld_st.h"
|
||||
|
||||
DEF_STRIDED_LD_ST_FORM_1(int64_t)
|
||||
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
|
||||
|
|
|
@ -1,11 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
|
||||
#include "strided_ld_st.h"
|
||||
|
||||
DEF_STRIDED_LD_ST_FORM_1(int8_t)
|
||||
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-assembler-times {vlse8.v} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsse8.v} 1 } } */
|
||||
|
|
|
@ -1,11 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
|
||||
#include "strided_ld_st.h"
|
||||
|
||||
DEF_STRIDED_LD_ST_FORM_1(uint16_t)
|
||||
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-assembler-times {vlse16.v} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsse16.v} 1 } } */
|
||||
|
|
|
@ -1,11 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
|
||||
#include "strided_ld_st.h"
|
||||
|
||||
DEF_STRIDED_LD_ST_FORM_1(uint32_t)
|
||||
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-assembler-times {vlse32.v} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsse32.v} 1 } } */
|
||||
|
|
|
@ -1,11 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
|
||||
#include "strided_ld_st.h"
|
||||
|
||||
DEF_STRIDED_LD_ST_FORM_1(uint64_t)
|
||||
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
|
||||
|
|
|
@ -1,11 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
|
||||
|
||||
#include "strided_ld_st.h"
|
||||
|
||||
DEF_STRIDED_LD_ST_FORM_1(uint8_t)
|
||||
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { xfail { any-opts "-O2" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { xfail { any-opts "-O3" } } } } */
|
||||
/* { dg-final { scan-assembler-times {vlse8.v} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsse8.v} 1 } } */
|
||||
|
|
Loading…
Add table
Reference in a new issue