arm.c (arm_function_ok_for_sibcall): Only forbid sibling calls for Thumb-1.
gcc/ * config/arm/arm.c (arm_function_ok_for_sibcall): Only forbid sibling calls for Thumb-1. * config/arm/arm.h (USE_RETURN_INSN): Enable for Thumb-2. * config/arm/arm.md (*call_symbol, *call_value_symbol): Use for Thumb-2. (*call_insn, *call_value_insn): Don't use for Thumb-2. (sibcall, sibcall_value, *sibcall_insn, *sibcall_value_insn): Use for Thumb-2. (return): New expander. (*arm_return): New name for ARM return insn. * config/arm/thumb2.md (*thumb2_return): New insn pattern. Co-Authored-By: Mark Mitchell <mark@codesourcery.com> From-SVN: r159672
This commit is contained in:
parent
204fc5505c
commit
7c19c715bb
5 changed files with 45 additions and 14 deletions
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@ -1,3 +1,18 @@
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2010-05-21 Julian Brown <julian@codesourcery.com>
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Mark Mitchell <mark@codesourcery.com>
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* config/arm/arm.c (arm_function_ok_for_sibcall): Only forbid
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sibling calls for Thumb-1.
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* config/arm/arm.h (USE_RETURN_INSN): Enable for Thumb-2.
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* config/arm/arm.md (*call_symbol, *call_value_symbol): Use for
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Thumb-2.
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(*call_insn, *call_value_insn): Don't use for Thumb-2.
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(sibcall, sibcall_value, *sibcall_insn, *sibcall_value_insn): Use
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for Thumb-2.
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(return): New expander.
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(*arm_return): New name for ARM return insn.
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* config/arm/thumb2.md (*thumb2_return): New insn pattern.
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2010-05-19 Joel Sherrill <joel.sherrill@oarcorp.com>
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* config.gcc (sparc64-*-rtems*): New target.
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@ -4794,8 +4794,8 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
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return false;
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/* Never tailcall something for which we have no decl, or if we
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are in Thumb mode. */
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if (decl == NULL || TARGET_THUMB)
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are generating code for Thumb-1. */
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if (decl == NULL || TARGET_THUMB1)
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return false;
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/* The PIC register is live on entry to VxWorks PLT entries, so we
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@ -1814,10 +1814,8 @@ typedef struct
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/* Determine if the epilogue should be output as RTL.
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You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
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/* This is disabled for Thumb-2 because it will confuse the
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conditional insn counter. */
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#define USE_RETURN_INSN(ISCOND) \
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(TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
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(TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
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/* Definitions for register eliminations.
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@ -8650,7 +8650,7 @@
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(match_operand 1 "" ""))
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(use (match_operand 2 "" ""))
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(clobber (reg:SI LR_REGNUM))]
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"TARGET_ARM
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"TARGET_32BIT
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&& (GET_CODE (operands[0]) == SYMBOL_REF)
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&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
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"*
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@ -8666,7 +8666,7 @@
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(match_operand:SI 2 "" "")))
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(use (match_operand 3 "" ""))
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(clobber (reg:SI LR_REGNUM))]
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"TARGET_ARM
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"TARGET_32BIT
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&& (GET_CODE (operands[1]) == SYMBOL_REF)
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&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
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"*
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@ -8681,7 +8681,7 @@
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(match_operand:SI 1 "" ""))
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(use (match_operand 2 "" ""))
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(clobber (reg:SI LR_REGNUM))]
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"TARGET_THUMB
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"TARGET_THUMB1
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&& GET_CODE (operands[0]) == SYMBOL_REF
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&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
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"bl\\t%a0"
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@ -8695,7 +8695,7 @@
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(match_operand 2 "" "")))
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(use (match_operand 3 "" ""))
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(clobber (reg:SI LR_REGNUM))]
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"TARGET_THUMB
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"TARGET_THUMB1
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&& GET_CODE (operands[1]) == SYMBOL_REF
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&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
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"bl\\t%a1"
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@ -8709,7 +8709,7 @@
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(match_operand 1 "general_operand" ""))
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(return)
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(use (match_operand 2 "" ""))])]
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"TARGET_ARM"
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"TARGET_32BIT"
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"
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{
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if (operands[2] == NULL_RTX)
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@ -8723,7 +8723,7 @@
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(match_operand 2 "general_operand" "")))
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(return)
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(use (match_operand 3 "" ""))])]
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"TARGET_ARM"
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"TARGET_32BIT"
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"
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{
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if (operands[3] == NULL_RTX)
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@ -8736,7 +8736,7 @@
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(match_operand 1 "" ""))
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(return)
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(use (match_operand 2 "" ""))]
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"TARGET_ARM && GET_CODE (operands[0]) == SYMBOL_REF"
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"TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF"
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"*
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return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\";
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"
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(match_operand 2 "" "")))
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(return)
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(use (match_operand 3 "" ""))]
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"TARGET_ARM && GET_CODE (operands[1]) == SYMBOL_REF"
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"TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF"
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"*
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return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\";
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"
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[(set_attr "type" "call")]
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)
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(define_expand "return"
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[(return)]
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"TARGET_32BIT && USE_RETURN_INSN (FALSE)"
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"")
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;; Often the return insn will be the same as loading from memory, so set attr
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(define_insn "return"
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(define_insn "*arm_return"
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[(return)]
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"TARGET_ARM && USE_RETURN_INSN (FALSE)"
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"*
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@ -1054,6 +1054,19 @@
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(set_attr "length" "20")]
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)
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;; Note: this is not predicable, to avoid issues with linker-generated
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;; interworking stubs.
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(define_insn "*thumb2_return"
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[(return)]
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"TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
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"*
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{
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return output_return_instruction (const_true_rtx, TRUE, FALSE);
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}"
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[(set_attr "type" "load1")
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(set_attr "length" "12")]
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)
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(define_insn_and_split "thumb2_eh_return"
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[(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
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VUNSPEC_EH_RETURN)
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