procyberian/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Sub-dword vector multiply for amdgcn

Browse source 
2019-12-13  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (mulv64si3<exec>): Rename to ...
	(mul<mode>3<exec>): ... this, and implement sub-dword patterns.
	(mulv64si3_dup<exec>): Rename to ...
	(mul<mode>3_dup<exec>): ... this, and implement sub-dword patterns.

From-SVN: r279374
This commit is contained in:
Andrew Stubbs 2019-12-13 16:37:17 +00:00 • committed by Andrew Stubbs
parent e44deb433b
commit 7b945b19ad
2 changed files with 18 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
gcc/ChangeLog
View file

@ -1,3 +1,10 @@
2019-12-13 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn-valu.md (mulv64si3<exec>): Rename to ...
(mul<mode>3<exec>): ... this, and implement sub-dword patterns.
(mulv64si3_dup<exec>): Rename to ...
(mul<mode>3_dup<exec>): ... this, and implement sub-dword patterns.
2019-12-13 Jan Hubicka <hubicka@ucw.cz>
* ipa-utils.c (ipa_merge_profiles): Improve dumping; merge common

22
gcc/config/gcn/gcn-valu.md
View file

@ -1740,22 +1740,22 @@
[(set_attr "type" "vop3a")
(set_attr "length" "8")])
(define_insn "mulv64si3<exec>"
[(set (match_operand:V64SI 0 "register_operand" "= v")
(mult:V64SI
(match_operand:V64SI 1 "gcn_alu_operand" "%vSvA")
(match_operand:V64SI 2 "gcn_alu_operand" " vSvA")))]
(define_insn "mul<mode>3<exec>"
[(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v")
(mult:VEC_ALL1REG_INT_MODE
(match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "%vSvA")
(match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_operand" " vSvA")))]
""
"v_mul_lo_u32\t%0, %1, %2"
[(set_attr "type" "vop3a")
(set_attr "length" "8")])
(define_insn "mulv64si3_dup<exec>"
[(set (match_operand:V64SI 0 "register_operand" "= v")
(mult:V64SI
(match_operand:V64SI 1 "gcn_alu_operand" "%vSvA")
(vec_duplicate:V64SI
(match_operand:SI 2 "gcn_alu_operand" " SvA"))))]
(define_insn "mul<mode>3_dup<exec>"
[(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v")
(mult:VEC_ALL1REG_INT_MODE
(match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "%vSvA")
(vec_duplicate:VEC_ALL1REG_INT_MODE
(match_operand:<SCALAR_MODE> 2 "gcn_alu_operand" " SvA"))))]
""
"v_mul_lo_u32\t%0, %1, %2"
[(set_attr "type" "vop3a")