invoke.texi: List r1x000 family under the -march MIPS option.
gcc/ 2008-10-06 Joshua Kinard <kumba@gentoo.org> * doc/invoke.texi: List r1x000 family under the -march MIPS option. * config/mips/mips.h (PROCESSOR_R10000): New processor_type. * config/mips/mips.c (mips_cpu_info_table): Add r10000, r12000, r14000 and r16000. (mips_rtx_cost_data): Add a PROCESSOR_R10000 entry. (mips_issue_rate): Handle PROCESSOR_R10000. * config/mips/mips.md (cpu): Add r10000. Include r10000.md. * config/mips/10000.md: New file. From-SVN: r140913
This commit is contained in:
Joshua Kinard
Richard Sandiford
parent
944258ebc6
commit
7a3446ec7c
6 changed files with 290 additions and 2 deletions
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@ -1,3 +1,15 @@
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2008-10-06 Joshua Kinard <kumba@gentoo.org>
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* doc/invoke.texi: List r1x000 family under the -march MIPS option.
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* config/mips/mips.h (PROCESSOR_R10000): New processor_type.
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* config/mips/mips.c (mips_cpu_info_table): Add r10000, r12000,
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r14000 and r16000.
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(mips_rtx_cost_data): Add a PROCESSOR_R10000 entry.
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(mips_issue_rate): Handle PROCESSOR_R10000.
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* config/mips/mips.md (cpu): Add r10000.
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Include r10000.md.
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* config/mips/10000.md: New file.
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2008-10-06 Richard Sandiford <rdsandiford@googlemail.com>
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* config/rs6000/rs6000-protos.h (rs6000_find_base_term): Declare.
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253
gcc/config/mips/10000.md
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253
gcc/config/mips/10000.md
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@ -0,0 +1,253 @@
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;; DFA-based pipeline description for the VR1x000.
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;; Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; R12K/R14K/R16K are derivatives of R10K, thus copy its description
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;; until specific tuning for each is added.
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;; R10000 has an int queue, fp queue, address queue.
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;; The int queue feeds ALU1 and ALU2.
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;; The fp queue feeds the fp-adder and fp-multiplier.
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;; The addr queue feeds the Load/Store unit.
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;;
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;; However, we define the fp-adder and fp-multiplier as
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;; separate automatons, because the fp-multiplier is
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;; divided into fp-multiplier, fp-division, and
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;; fp-squareroot units, all of which share the same
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;; issue and completion logic, yet can operate in
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;; parallel.
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;;
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;; This is based on the model described in the R10K Manual
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;; and it helps to reduce the size of the automata.
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(define_automaton "r10k_a_int, r10k_a_fpadder, r10k_a_addr,
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r10k_a_fpmpy, r10k_a_fpdiv, r10k_a_fpsqrt")
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(define_cpu_unit "r10k_alu1" "r10k_a_int")
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(define_cpu_unit "r10k_alu2" "r10k_a_int")
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(define_cpu_unit "r10k_fpadd" "r10k_a_fpadder")
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(define_cpu_unit "r10k_fpmpy" "r10k_a_fpmpy")
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(define_cpu_unit "r10k_fpdiv" "r10k_a_fpdiv")
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(define_cpu_unit "r10k_fpsqrt" "r10k_a_fpsqrt")
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(define_cpu_unit "r10k_loadstore" "r10k_a_addr")
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;; R10k Loads and Stores.
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(define_insn_reservation "r10k_load" 2
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(and (eq_attr "cpu" "r10000")
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(eq_attr "type" "load,prefetch,prefetchx"))
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"r10k_loadstore")
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(define_insn_reservation "r10k_store" 0
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(and (eq_attr "cpu" "r10000")
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(eq_attr "type" "store,fpstore,fpidxstore"))
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"r10k_loadstore")
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(define_insn_reservation "r10k_fpload" 3
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(and (eq_attr "cpu" "r10000")
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(eq_attr "type" "fpload,fpidxload"))
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"r10k_loadstore")
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;; Integer add/sub + logic ops, and mt hi/lo can be done by alu1 or alu2.
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;; Miscellaneous arith goes here too (this is a guess).
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(define_insn_reservation "r10k_arith" 1
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(and (eq_attr "cpu" "r10000")
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(eq_attr "type" "arith,mthilo,slt,clz,const,nop,trap,logical"))
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"r10k_alu1 | r10k_alu2")
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;; We treat mfhilo differently, because we need to know when
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;; it's HI and when it's LO.
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(define_insn_reservation "r10k_mfhi" 1
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "mfhilo")
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(not (match_operand 1 "lo_operand"))))
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"r10k_alu1 | r10k_alu2")
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(define_insn_reservation "r10k_mflo" 1
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "mfhilo")
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(match_operand 1 "lo_operand")))
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"r10k_alu1 | r10k_alu2")
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;; ALU1 handles shifts, branch eval, and condmove.
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;;
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;; Brancher is separate, but part of ALU1, but can only
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;; do one branch per cycle (is this even implementable?).
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;;
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;; Unsure if the brancher handles jumps and calls as well, but since
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;; they're related, we'll add them here for now.
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(define_insn_reservation "r10k_brancher" 1
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(and (eq_attr "cpu" "r10000")
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(eq_attr "type" "shift,branch,jump,call"))
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"r10k_alu1")
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(define_insn_reservation "r10k_int_cmove" 1
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "condmove")
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(eq_attr "mode" "SI,DI")))
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"r10k_alu1")
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;; Coprocessor Moves.
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;; mtc1/dmtc1 are handled by ALU1.
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;; mfc1/dmfc1 are handled by the fp-multiplier.
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(define_insn_reservation "r10k_mt_xfer" 3
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(and (eq_attr "cpu" "r10000")
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(eq_attr "type" "mtc"))
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"r10k_alu1")
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(define_insn_reservation "r10k_mf_xfer" 2
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(and (eq_attr "cpu" "r10000")
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(eq_attr "type" "mfc"))
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"r10k_fpmpy")
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;; Only ALU2 does int multiplications and divisions.
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;;
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;; According to the Vr10000 series user manual,
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;; integer mult and div insns can be issued one
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;; cycle earlier if using register Lo. We model
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;; this by using the Lo value by default, as it
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;; is the more common value, and use a bypass
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;; for the Hi value when needed.
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;;
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;; Also of note, There are different latencies
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;; for MULT/DMULT (Lo 5/Hi 6) and MULTU/DMULTU (Lo 6/Hi 7).
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;; However, gcc does not have separate types
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;; for these insns. Thus to strike a balance,
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;; we use the Hi latency value for imul
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;; operations until the imul type can be split.
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(define_insn_reservation "r10k_imul_single" 6
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "imul,imul3")
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(eq_attr "mode" "SI")))
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"r10k_alu2 * 6")
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(define_insn_reservation "r10k_imul_double" 10
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "imul,imul3")
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(eq_attr "mode" "DI")))
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"r10k_alu2 * 10")
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;; Divides keep ALU2 busy.
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(define_insn_reservation "r10k_idiv_single" 34
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "SI")))
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"r10k_alu2 * 35")
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(define_insn_reservation "r10k_idiv_double" 66
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "DI")))
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"r10k_alu2 * 67")
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(define_bypass 35 "r10k_idiv_single" "r10k_mfhi")
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(define_bypass 67 "r10k_idiv_double" "r10k_mfhi")
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;; Floating point add/sub, mul, abs value, neg, comp, & moves.
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(define_insn_reservation "r10k_fp_miscadd" 2
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(and (eq_attr "cpu" "r10000")
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(eq_attr "type" "fadd,fabs,fneg,fcmp"))
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"r10k_fpadd")
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(define_insn_reservation "r10k_fp_miscmul" 2
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(and (eq_attr "cpu" "r10000")
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(eq_attr "type" "fmul,fmove"))
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"r10k_fpmpy")
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(define_insn_reservation "r10k_fp_cmove" 2
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "condmove")
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(eq_attr "mode" "SF,DF")))
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"r10k_fpmpy")
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;; The fcvt.s.[wl] insn has latency 4, repeat 2.
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;; All other fcvt insns have latency 2, repeat 1.
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(define_insn_reservation "r10k_fcvt_single" 4
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "fcvt")
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(eq_attr "cnv_mode" "I2S")))
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"r10k_fpadd * 2")
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(define_insn_reservation "r10k_fcvt_other" 2
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "fcvt")
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(eq_attr "cnv_mode" "!I2S")))
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"r10k_fpadd")
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;; Run the fmadd insn through fp-adder first, then fp-multiplier.
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;;
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;; The latency for fmadd is 2 cycles if the result is used
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;; by another fmadd instruction.
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(define_insn_reservation "r10k_fmadd" 4
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(and (eq_attr "cpu" "r10000")
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(eq_attr "type" "fmadd"))
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"r10k_fpadd, r10k_fpmpy")
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(define_bypass 2 "r10k_fmadd" "r10k_fmadd")
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;; Floating point Divisions & square roots.
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(define_insn_reservation "r10k_fdiv_single" 12
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "fdiv,frdiv")
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(eq_attr "mode" "SF")))
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"r10k_fpdiv * 14")
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(define_insn_reservation "r10k_fdiv_double" 19
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "fdiv,frdiv")
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(eq_attr "mode" "DF")))
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"r10k_fpdiv * 21")
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(define_insn_reservation "r10k_fsqrt_single" 18
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "fsqrt")
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(eq_attr "mode" "SF")))
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"r10k_fpsqrt * 20")
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(define_insn_reservation "r10k_fsqrt_double" 33
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "fsqrt")
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(eq_attr "mode" "DF")))
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"r10k_fpsqrt * 35")
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(define_insn_reservation "r10k_frsqrt_single" 30
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "SF")))
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"r10k_fpsqrt * 20")
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(define_insn_reservation "r10k_frsqrt_double" 52
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(and (eq_attr "cpu" "r10000")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "DF")))
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"r10k_fpsqrt * 35")
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;; Handle unknown/multi insns here (this is a guess).
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(define_insn_reservation "r10k_unknown" 1
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(and (eq_attr "cpu" "r10000")
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(eq_attr "type" "unknown,multi"))
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"r10k_alu1 + r10k_alu2")
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@ -607,6 +607,10 @@ static const struct mips_cpu_info mips_cpu_info_table[] = {
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/* MIPS IV processors. */
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{ "r8000", PROCESSOR_R8000, 4, 0 },
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{ "r10000", PROCESSOR_R10000, 4, 0 },
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{ "r12000", PROCESSOR_R10000, 4, 0 },
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{ "r14000", PROCESSOR_R10000, 4, 0 },
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{ "r16000", PROCESSOR_R10000, 4, 0 },
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{ "vr5000", PROCESSOR_R5000, 4, 0 },
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{ "vr5400", PROCESSOR_R5400, 4, 0 },
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{ "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
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@ -1015,6 +1019,19 @@ static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
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1, /* branch_cost */
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4 /* memory_latency */
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},
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{ /* R1x000 */
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COSTS_N_INSNS (2), /* fp_add */
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COSTS_N_INSNS (2), /* fp_mult_sf */
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COSTS_N_INSNS (2), /* fp_mult_df */
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COSTS_N_INSNS (12), /* fp_div_sf */
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COSTS_N_INSNS (19), /* fp_div_df */
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COSTS_N_INSNS (5), /* int_mult_si */
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COSTS_N_INSNS (9), /* int_mult_di */
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COSTS_N_INSNS (34), /* int_div_si */
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COSTS_N_INSNS (66), /* int_div_di */
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1, /* branch_cost */
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4 /* memory_latency */
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},
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{ /* SB1 */
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/* These costs are the same as the SB-1A below. */
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COSTS_N_INSNS (4), /* fp_add */
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@ -10369,7 +10386,10 @@ mips_issue_rate (void)
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but in reality only a maximum of 3 insns can be issued as
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floating-point loads and stores also require a slot in the
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AGEN pipe. */
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return 4;
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case PROCESSOR_R10000:
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/* All R10K Processors are quad-issue (being the first MIPS
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processors to support this feature). */
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return 4;
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case PROCESSOR_20KC:
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case PROCESSOR_R4130:
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@ -67,6 +67,7 @@ enum processor_type {
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PROCESSOR_R7000,
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PROCESSOR_R8000,
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PROCESSOR_R9000,
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PROCESSOR_R10000,
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PROCESSOR_SB1,
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PROCESSOR_SB1A,
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PROCESSOR_SR71000,
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@ -560,7 +560,7 @@
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;; Attribute describing the processor. This attribute must match exactly
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;; with the processor_type enumeration in mips.h.
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(define_attr "cpu"
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"r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000,xlr"
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"r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sb1a,sr71000,xlr"
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(const (symbol_ref "mips_tune")))
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;; The type of hardware hazard associated with this instruction.
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@ -935,6 +935,7 @@
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(include "6000.md")
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(include "7000.md")
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(include "9000.md")
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(include "10000.md")
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(include "loongson2ef.md")
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(include "octeon.md")
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(include "sb1.md")
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@ -12231,6 +12231,7 @@ The processor names are:
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@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
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@samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000},
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@samp{rm7000}, @samp{rm9000},
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@samp{r10000}, @samp{r12000}, @samp{r14000}, @samp{r16000},
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@samp{sb1},
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@samp{sr71000},
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@samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
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