arm.c, [...]: Fix comment typos.
* config/arm/arm.c, config/arm/arm.h, config/arm/arm.md, config/arm/thumb2.md: Fix comment typos. * doc/extend.texi: Fix a typo. From-SVN: r120566
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
cf7cf214f2
commit
7a085dce62
6 changed files with 23 additions and 17 deletions
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@ -1,3 +1,9 @@
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2007-01-08 Kazu Hirata <kazu@codesourcery.com>
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* config/arm/arm.c, config/arm/arm.h, config/arm/arm.md,
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config/arm/thumb2.md: Fix comment typos.
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* doc/extend.texi: Fix a typo.
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2007-01-07 Eric Christopher <echristo@apple.com>
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* configure.ac: Check for __stack_chk_fail for darwin.
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@ -449,7 +449,7 @@ static int thumb_call_reg_needed;
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#define FL_THUMB2 (1 << 16) /* Thumb-2. */
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#define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
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profile. */
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#define FL_DIV (1 << 18) /* Hardware divde. */
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#define FL_DIV (1 << 18) /* Hardware divide. */
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#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
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@ -2501,7 +2501,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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else
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i -= 7;
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}
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/* Arm allows rotates by a multiple of two. Thumb-2 allows arbitary
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/* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
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shifts. */
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if (TARGET_ARM)
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i -= 2;
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@ -7702,11 +7702,11 @@ get_jump_table_size (rtx insn)
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switch (modesize)
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{
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case 1:
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/* Round up size of TBB table to a hafword boundary. */
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/* Round up size of TBB table to a haflword boundary. */
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size = (size + 1) & ~(HOST_WIDE_INT)1;
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break;
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case 2:
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/* No padding neccessary for TBH. */
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/* No padding necessary for TBH. */
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break;
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case 4:
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/* Add two bytes for alignment on Thumb. */
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@ -10448,7 +10448,7 @@ arm_output_epilogue (rtx sibling)
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if (frame_pointer_needed)
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{
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/* For Thumb-2 restore sp from the frame pointer.
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Operand restrictions mean we have to incrememnt FP, then copy
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Operand restrictions mean we have to increment FP, then copy
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to SP. */
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amount = offsets->locals_base - offsets->saved_regs;
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operands[0] = hard_frame_pointer_rtx;
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@ -11116,7 +11116,7 @@ arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
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}
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/* Emit RTL to save coprocessor registers on funciton entry. Returns the
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/* Emit RTL to save coprocessor registers on function entry. Returns the
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number of bytes pushed. */
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static int
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@ -11592,7 +11592,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
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case '.':
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/* The current condition code for a condition code setting instruction.
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Preceeded by 's' in unified syntax, otherwise followed by 's'. */
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Preceded by 's' in unified syntax, otherwise followed by 's'. */
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if (TARGET_UNIFIED_ASM)
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{
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fputc('s', stream);
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@ -12240,7 +12240,7 @@ thumb2_final_prescan_insn (rtx insn)
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continue;
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}
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/* ??? Recognise conditional jumps, and combine them with IT blocks. */
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/* ??? Recognize conditional jumps, and combine them with IT blocks. */
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if (GET_CODE (body) != COND_EXEC)
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break;
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/* Allow up to 4 conditionally executed instructions in a block. */
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@ -16473,7 +16473,7 @@ arm_output_addr_const_extra (FILE *fp, rtx x)
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/* Output assembly for a shift instruction.
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SET_FLAGS determines how the instruction modifies the condition codes.
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0 - Do not set conditiona codes.
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0 - Do not set condition codes.
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1 - Set condition codes.
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2 - Use smallest instruction. */
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const char *
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@ -1881,7 +1881,7 @@ typedef struct
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#define ASM_OUTPUT_LABELREF(FILE, NAME) \
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arm_asm_output_labelref (FILE, NAME)
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/* Output IT instructions for conditonally executed Thumb-2 instructions. */
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/* Output IT instructions for conditionally executed Thumb-2 instructions. */
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#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
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if (TARGET_THUMB2) \
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thumb2_asm_output_opcode (STREAM);
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@ -1962,7 +1962,7 @@ typedef struct
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The usual definition accepts all pseudo regs; the other rejects
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them unless they have been allocated suitable hard regs.
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The symbol REG_OK_STRICT causes the latter definition to be used.
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Thumb-2 has the same restictions as arm. */
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Thumb-2 has the same restrictions as arm. */
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#ifndef REG_OK_STRICT
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#define ARM_REG_OK_FOR_BASE_P(X) \
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@ -10518,8 +10518,8 @@
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/* For the StrongARM at least it is faster to
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use STR to store only a single register.
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In Thumb mode always use push, and the assmebler will pick
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something approporiate. */
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In Thumb mode always use push, and the assembler will pick
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something appropriate. */
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if (num_saves == 1 && TARGET_ARM)
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output_asm_insn (\"str\\t%1, [%m0, #-4]!\", operands);
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else
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@ -277,7 +277,7 @@
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)
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;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
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;; of the messyness assocuated with the ARM patterns.
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;; of the messyness associated with the ARM patterns.
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(define_insn "*thumb2_movhi_insn"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
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(match_operand:HI 1 "general_operand" "rI,n,r,m"))]
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@ -858,7 +858,7 @@
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"TARGET_THUMB2"
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"*
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/* ??? Output both instructions unconditionally, otherwise the conditional
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executon insn counter gets confused.
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execution insn counter gets confused.
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if (REGNO (operands[1])
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!= REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) */
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output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
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@ -890,7 +890,7 @@
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"TARGET_THUMB2"
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"*
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/* ??? Output both instructions unconditionally, otherwise the conditional
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executon insn counter gets confused.
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execution insn counter gets confused.
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if (REGNO (operands[1])
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!= REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) */
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output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
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@ -1965,7 +1965,7 @@ void f () __attribute__ ((interrupt ("IRQ")));
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Permissible values for this parameter are: IRQ, FIQ, SWI, ABORT and UNDEF@.
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On ARMv7-M the interrupt type is ignored, and the attibute means the function
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On ARMv7-M the interrupt type is ignored, and the attribute means the function
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may be called with a word aligned stack pointer.
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@item interrupt_handler
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