[ARC] Add support for advanced mpy/mac instructions.
gcc/ 2017-05-09 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (arc_conditional_register_usage): Handle ACCL, ACCH registers. * config/arc/arc.md (mulsidi3): Use advanced mpy instructions when available. (umulsidi3): Likewise. (mulsidi3_700): Disable this pattern when we have advanced mpy instructions. (umulsidi3_700): Likewise. (maddsidi4): New pattern. (macd, mac, mac_r, umaddsidi4, macdu, macu, macu_r): Likewise. (mpyd_arcv2hs, mpyd_imm_arcv2hs, mpydu_arcv2hs): Likewise. (mpydu_imm_arcv2hs): Likewise. * config/arc/predicates.md (accl_operand): New predicate. From-SVN: r247797
This commit is contained in:
Claudiu Zissulescu
Claudiu Zissulescu
parent
c7314bc17b
commit
79557baea8
8 changed files with 341 additions and 4 deletions
16
ChangeLog
16
ChangeLog
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@ -1,3 +1,19 @@
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2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc.c (arc_conditional_register_usage): Handle ACCL,
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ACCH registers.
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* config/arc/arc.md (mulsidi3): Use advanced mpy instructions when
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available.
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(umulsidi3): Likewise.
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(mulsidi3_700): Disable this pattern when we have advanced mpy
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instructions.
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(umulsidi3_700): Likewise.
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(maddsidi4): New pattern.
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(macd, mac, mac_r, umaddsidi4, macdu, macu, macu_r): Likewise.
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(mpyd_arcv2hs, mpyd_imm_arcv2hs, mpydu_arcv2hs): Likewise.
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(mpydu_imm_arcv2hs): Likewise.
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* config/arc/predicates.md (accl_operand): New predicate.
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2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
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Andrew Burgess <andrew.burgess@embecosm.com>
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@ -1786,8 +1786,9 @@ arc_conditional_register_usage (void)
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arc_regno_reg_class[PROGRAM_COUNTER_REGNO] = GENERAL_REGS;
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/*ARCV2 Accumulator. */
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if (TARGET_V2
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&& (TARGET_FP_DP_FUSED || TARGET_FP_SP_FUSED))
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if ((TARGET_V2
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&& (TARGET_FP_DP_FUSED || TARGET_FP_SP_FUSED))
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|| TARGET_PLUS_DMPY)
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{
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arc_regno_reg_class[ACCL_REGNO] = WRITABLE_CORE_REGS;
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arc_regno_reg_class[ACCH_REGNO] = WRITABLE_CORE_REGS;
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@ -2157,6 +2157,18 @@
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"TARGET_ANY_MPY"
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"
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{
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if (TARGET_PLUS_MACD)
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{
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if (CONST_INT_P (operands[2]))
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{
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emit_insn (gen_mpyd_imm_arcv2hs (operands[0], operands[1], operands[2]));
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}
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else
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{
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emit_insn (gen_mpyd_arcv2hs (operands[0], operands[1], operands[2]));
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}
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DONE;
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}
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if (TARGET_MPY)
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{
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operands[2] = force_reg (SImode, operands[2]);
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@ -2237,7 +2249,7 @@
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[(set (match_operand:DI 0 "register_operand" "=&r")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%c"))
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(sign_extend:DI (match_operand:SI 2 "extend_operand" "cL"))))]
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"TARGET_MPY"
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"TARGET_MPY && !TARGET_PLUS_MACD"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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@ -2390,6 +2402,18 @@
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(zero_extend:DI (match_operand:SI 2 "nonmemory_operand" ""))))]
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""
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{
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if (TARGET_PLUS_MACD)
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{
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if (CONST_INT_P (operands[2]))
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{
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emit_insn (gen_mpydu_imm_arcv2hs (operands[0], operands[1], operands[2]));
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}
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else
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{
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emit_insn (gen_mpydu_arcv2hs (operands[0], operands[1], operands[2]));
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}
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DONE;
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}
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if (TARGET_MPY)
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{
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operands[2] = force_reg (SImode, operands[2]);
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@ -2480,7 +2504,7 @@
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[(set (match_operand:DI 0 "dest_reg_operand" "=&r")
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(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%c"))
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(zero_extend:DI (match_operand:SI 2 "extend_operand" "cL"))))]
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"TARGET_MPY"
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"TARGET_MPY && !TARGET_PLUS_MACD"
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"#"
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"reload_completed"
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[(const_int 0)]
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@ -6248,6 +6272,244 @@
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""
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[(set_attr "length" "0")])
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;; MAC and DMPY instructions
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(define_insn_and_split "maddsidi4"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI
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(mult:DI
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(sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
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(sign_extend:DI (match_operand:SI 2 "extend_operand" "ri")))
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(match_operand:DI 3 "register_operand" "r")))]
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"TARGET_PLUS_DMPY"
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"#"
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"TARGET_PLUS_DMPY && reload_completed"
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[(const_int 0)]
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"{
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rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
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emit_move_insn (acc_reg, operands[3]);
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if (TARGET_PLUS_MACD)
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emit_insn (gen_macd (operands[0], operands[1], operands[2]));
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else
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{
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emit_insn (gen_mac (operands[1], operands[2]));
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emit_move_insn (operands[0], acc_reg);
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}
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DONE;
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}"
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[(set_attr "type" "multi")
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(set_attr "length" "36")])
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(define_insn "macd"
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[(set (match_operand:DI 0 "even_register_operand" "=Rcr,r,r")
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(plus:DI
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(mult:DI
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(sign_extend:DI (match_operand:SI 1 "register_operand" "%0,c,c"))
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(sign_extend:DI (match_operand:SI 2 "extend_operand" " c,cI,Cal")))
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(reg:DI ARCV2_ACC)))
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(set (reg:DI ARCV2_ACC)
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(plus:DI
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(mult:DI (sign_extend:DI (match_dup 1))
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(sign_extend:DI (match_dup 2)))
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(reg:DI ARCV2_ACC)))]
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"TARGET_PLUS_MACD"
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"macd %0,%1,%2"
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[(set_attr "length" "4,4,8")
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(set_attr "type" "multi")
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(set_attr "predicable" "yes,no,no")
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(set_attr "cond" "canuse,nocond,nocond")])
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(define_insn "mac"
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[(set (reg:DI ARCV2_ACC)
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(plus:DI
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(mult:DI (sign_extend:DI (match_operand:SI 0 "register_operand" "%r,r"))
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(sign_extend:DI (match_operand:SI 1 "extend_operand" "rI,i")))
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(reg:DI ARCV2_ACC)))]
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"TARGET_PLUS_DMPY"
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"mac 0,%0,%1"
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[(set_attr "length" "4,8")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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(set_attr "cond" "nocond")])
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(define_peephole2
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[(set (reg:DI ARCV2_ACC)
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(plus:DI
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(mult:DI (sign_extend:DI (match_operand:SI 0 "register_operand" ""))
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(sign_extend:DI (match_operand:SI 1 "extend_operand" "")))
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(reg:DI ARCV2_ACC)))
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(set (match_operand:SI 2 "register_operand" "")
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(match_operand:SI 3 "accl_operand" ""))]
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"TARGET_PLUS_DMPY"
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[(const_int 0)]
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{
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emit_insn (gen_mac_r (operands[2], operands[0], operands[1]));
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DONE;
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})
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(define_insn "mac_r"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(truncate:SI
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(plus:DI
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(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r,r"))
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(sign_extend:DI (match_operand:SI 2 "extend_operand" "rI,i")))
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(reg:DI ARCV2_ACC))))
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(clobber (reg:DI ARCV2_ACC))]
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"TARGET_PLUS_DMPY"
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"mac %0,%1,%2"
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[(set_attr "length" "4,8")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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(set_attr "cond" "nocond")])
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(define_insn_and_split "umaddsidi4"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI
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(mult:DI
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(zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
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(zero_extend:DI (match_operand:SI 2 "extend_operand" "ri")))
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(match_operand:DI 3 "register_operand" "r")))]
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"TARGET_PLUS_DMPY"
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"#"
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"TARGET_PLUS_DMPY && reload_completed"
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[(const_int 0)]
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"{
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rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
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emit_move_insn (acc_reg, operands[3]);
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if (TARGET_PLUS_MACD)
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emit_insn (gen_macdu (operands[0], operands[1], operands[2]));
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else
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{
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emit_insn (gen_macu (operands[1], operands[2]));
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emit_move_insn (operands[0], acc_reg);
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}
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DONE;
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}"
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[(set_attr "type" "multi")
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(set_attr "length" "36")])
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(define_insn "macdu"
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[(set (match_operand:DI 0 "even_register_operand" "=Rcr,r,r")
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(plus:DI
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(mult:DI
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(zero_extend:DI (match_operand:SI 1 "register_operand" "%0,c,c"))
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(zero_extend:DI (match_operand:SI 2 "extend_operand" " c,cI,i")))
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(reg:DI ARCV2_ACC)))
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(set (reg:DI ARCV2_ACC)
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(plus:DI
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(mult:DI (zero_extend:DI (match_dup 1))
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(zero_extend:DI (match_dup 2)))
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(reg:DI ARCV2_ACC)))]
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"TARGET_PLUS_MACD"
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"macdu %0,%1,%2"
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[(set_attr "length" "4,4,8")
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(set_attr "type" "multi")
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(set_attr "predicable" "yes,no,no")
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(set_attr "cond" "canuse,nocond,nocond")])
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(define_insn "macu"
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[(set (reg:DI ARCV2_ACC)
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(plus:DI
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(mult:DI (zero_extend:DI (match_operand:SI 0 "register_operand" "%r,r"))
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(zero_extend:DI (match_operand:SI 1 "extend_operand" "rI,i")))
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(reg:DI ARCV2_ACC)))]
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"TARGET_PLUS_DMPY"
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"macu 0,%0,%1"
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[(set_attr "length" "4,8")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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(set_attr "cond" "nocond")])
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(define_peephole2
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[(set (reg:DI ARCV2_ACC)
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(plus:DI
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(mult:DI (zero_extend:DI (match_operand:SI 0 "register_operand" ""))
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(zero_extend:DI (match_operand:SI 1 "extend_operand" "")))
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(reg:DI ARCV2_ACC)))
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(set (match_operand:SI 2 "register_operand" "")
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(match_operand:SI 3 "accl_operand" ""))]
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"TARGET_PLUS_DMPY"
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[(const_int 0)]
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{
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emit_insn (gen_macu_r (operands[2], operands[0], operands[1]));
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DONE;
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})
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(define_insn "macu_r"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(truncate:SI
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(plus:DI
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(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r,r"))
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(zero_extend:DI (match_operand:SI 2 "extend_operand" "rI,i")))
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(reg:DI ARCV2_ACC))))
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(clobber (reg:DI ARCV2_ACC))]
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"TARGET_PLUS_DMPY"
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"macu %0,%1,%2"
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[(set_attr "length" "4,8")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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(set_attr "cond" "nocond")])
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(define_insn "mpyd_arcv2hs"
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[(set (match_operand:DI 0 "even_register_operand" "=Rcr, r")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " 0, c"))
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(sign_extend:DI (match_operand:SI 2 "register_operand" " c, c"))))
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(set (reg:DI ARCV2_ACC)
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(mult:DI
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(sign_extend:DI (match_dup 1))
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(sign_extend:DI (match_dup 2))))]
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"TARGET_PLUS_MACD"
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"mpyd%? %0,%1,%2"
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[(set_attr "length" "4,4")
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(set_attr "iscompact" "false")
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(set_attr "type" "multi")
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(set_attr "predicable" "yes,no")
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(set_attr "cond" "canuse,nocond")])
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(define_insn "mpyd_imm_arcv2hs"
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[(set (match_operand:DI 0 "even_register_operand" "=Rcr, r,r,Rcr, r")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " 0, c,0, 0, c"))
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(match_operand 2 "immediate_operand" " L, L,I,Cal,Cal")))
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(set (reg:DI ARCV2_ACC)
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(mult:DI (sign_extend:DI (match_dup 1))
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(match_dup 2)))]
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"TARGET_PLUS_MACD"
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"mpyd%? %0,%1,%2"
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[(set_attr "length" "4,4,4,8,8")
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(set_attr "iscompact" "false")
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(set_attr "type" "multi")
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(set_attr "predicable" "yes,no,no,yes,no")
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(set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond")])
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(define_insn "mpydu_arcv2hs"
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[(set (match_operand:DI 0 "even_register_operand" "=Rcr, r")
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(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " 0, c"))
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(zero_extend:DI (match_operand:SI 2 "register_operand" " c, c"))))
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(set (reg:DI ARCV2_ACC)
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(mult:DI (zero_extend:DI (match_dup 1))
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(zero_extend:DI (match_dup 2))))]
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"TARGET_PLUS_MACD"
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"mpydu%? %0,%1,%2"
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[(set_attr "length" "4,4")
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(set_attr "iscompact" "false")
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(set_attr "type" "multi")
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(set_attr "predicable" "yes,no")
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(set_attr "cond" "canuse,nocond")])
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(define_insn "mpydu_imm_arcv2hs"
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[(set (match_operand:DI 0 "even_register_operand" "=Rcr, r,r,Rcr, r")
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(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " 0, c,0, 0, c"))
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(match_operand 2 "immediate_operand" " L, L,I,Cal,Cal")))
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(set (reg:DI ARCV2_ACC)
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(mult:DI (zero_extend:DI (match_dup 1))
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(match_dup 2)))]
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"TARGET_PLUS_MACD"
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"mpydu%? %0,%1,%2"
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[(set_attr "length" "4,4,4,8,8")
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(set_attr "iscompact" "false")
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(set_attr "type" "multi")
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(set_attr "predicable" "yes,no,no,yes,no")
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(set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond")])
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;; include the arc-FPX instructions
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(include "fpx.md")
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@ -697,6 +697,11 @@
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(and (match_code "reg")
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(match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 58 : 59)")))
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(define_predicate "accl_operand"
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(and (match_code "reg")
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(match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 59 : 58)")
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(match_test "TARGET_V2")))
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; Unfortunately, we can not allow a const_int_operand before reload, because
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; reload needs a non-void mode to guide it how to reload the inside of a
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; {sign_}extend.
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@ -1,3 +1,9 @@
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2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
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* gcc.target/arc/tmac-1.c: New file.
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* gcc.target/arc/tmac-2.c: Likewise.
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* gcc.target/arc/tmac.h: Likewise.
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2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
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Andrew Burgess <andrew.burgess@embecosm.com>
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12
gcc/testsuite/gcc.target/arc/tmac-1.c
Normal file
12
gcc/testsuite/gcc.target/arc/tmac-1.c
Normal file
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@ -0,0 +1,12 @@
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/* { dg-skip-if "" { ! { clmcpu } } } */
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/* { dg-do compile } */
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/* { dg-options "-O2 -mcpu=archs -mmpy-option=8" } */
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/* Test MAC operation for MPY_OPTION = 8. */
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#include "tmac.h"
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/* { dg-final { scan-assembler "macd " } } */
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/* { dg-final { scan-assembler "macdu" } } */
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/* { dg-final { scan-assembler "mpyd " } } */
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/* { dg-final { scan-assembler "mpydu" } } */
|
||||
|
||||
11
gcc/testsuite/gcc.target/arc/tmac-2.c
Normal file
11
gcc/testsuite/gcc.target/arc/tmac-2.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-skip-if "" { ! { clmcpu } } } */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mcpu=archs -mmpy-option=7" } */
|
||||
|
||||
/* Test MAC operation for MPY_OPTION = 7. */
|
||||
#include "tmac.h"
|
||||
|
||||
/* { dg-final { scan-assembler "mac " } } */
|
||||
/* { dg-final { scan-assembler "macu" } } */
|
||||
/* { dg-final { scan-assembler "mpym " } } */
|
||||
/* { dg-final { scan-assembler "mpymu" } } */
|
||||
24
gcc/testsuite/gcc.target/arc/tmac.h
Normal file
24
gcc/testsuite/gcc.target/arc/tmac.h
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/* Test MAC operations. */
|
||||
|
||||
long long foo (long long a, int b, int c)
|
||||
{
|
||||
a += (long long )c * (long long )b;
|
||||
return a;
|
||||
}
|
||||
|
||||
long long foo1 (int b, int c)
|
||||
{
|
||||
return (long long)c * (long long) b;
|
||||
}
|
||||
|
||||
long long foo3 (long long a, unsigned int b, unsigned int c)
|
||||
{
|
||||
a += (unsigned long long )c * (unsigned long long )b;
|
||||
return a;
|
||||
}
|
||||
|
||||
long long foo4 (unsigned int b, unsigned int c)
|
||||
{
|
||||
return (unsigned long long)c * (unsigned long long) b;
|
||||
}
|
||||
|
||||
Loading…
Add table
Reference in a new issue