From 78d8c16ca93453666755e70c5931bffda080d12c Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Tue, 23 Aug 2011 22:00:27 +0200 Subject: [PATCH] constraints.md (Yp): New register constraint. * config/i386/constraints.md (Yp): New register constraint. * config/i386/i386.md (*addhi_1): Merge with *addhi_1_lea using Yp register constraint. (*addqi_1): Merge with *addqi_1_lea using Yp register constraint. (*ashlhi3_1): Merge with *ashlhi3_1_lea using Yp register constraint. (*ashlqi3_1): Merge with *ashlqi3_1_lea using Yp register constraint. From-SVN: r178011 --- gcc/ChangeLog | 34 +++--- gcc/config/i386/constraints.md | 7 ++ gcc/config/i386/i386.md | 214 +++------------------------------ 3 files changed, 40 insertions(+), 215 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1b5e9ead502..8b8ba626270 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2011-08-23 Uros Bizjak + + * config/i386/constraints.md (Yp): New register constraint. + * config/i386/i386.md (*addhi_1): Merge with *addhi_1_lea using + Yp register constraint. + (*addqi_1): Merge with *addqi_1_lea using Yp register constraint. + (*ashlhi3_1): Merge with *ashlhi3_1_lea using Yp register constraint. + (*ashlqi3_1): Merge with *ashlqi3_1_lea using Yp register constraint. + 2011-08-23 Kirill Yukhin * config/i386/sse.md (mul3_highpart): Update. @@ -18,21 +27,17 @@ (imm_disp): Ditto. (isa): Add bmi2. (enabled): Handle bmi2. - (w): New mode attribute. (*mul3): Split from *mul3. (*umul3): Ditto. Add imulx BMI2 alternative. (*bmi2_umulditi3_1): New insn pattern. (*bmi2_umulsidi3_1): Ditto. - (*umul3 splitter): New splitter to avoid flags - dependency. + (*umul3 splitter): New splitter to avoid flags dependency. (*bmi2_ashl3_1): New insn pattern. (*ashl3_1): Add ishiftx BMI2 alternative. - (*ashl3_1 splitter): New splitter to avoid flags - dependency. + (*ashl3_1 splitter): New splitter to avoid flags dependency. (*bmi2_ashlsi3_1_zext): New insn pattern. (*ashlsi3_1_zext): Add ishiftx BMI2 alternative. - (*ashlsi3_1_zext splitter): New splitter to avoid flags - dependency. + (*ashlsi3_1_zext splitter): New splitter to avoid flags dependency. (*bmi2_3_1): New insn pattern. (*3_1): Add ishiftx BMI2 alternative. (*3_1 splitter): New splitter to avoid @@ -43,19 +48,16 @@ flags dependency. (*bmi2_rorx3_1): New insn pattern. (*3_1): Add rotatex BMI2 alternative. - (*rotate3_1 splitter): New splitter to avoid flags - dependency. + (*rotate3_1 splitter): New splitter to avoid flags dependency. (*rotatert3_1 splitter): Ditto. (*bmi2_rorxsi3_1_zext): New insn pattern. (*si3_1_zext): Add rotatex BMI2 alternative. - (*rotatesi3_1_zext splitter): New splitter to avoid flags - dependency. + (*rotatesi3_1_zext splitter): New splitter to avoid flags dependency. (*rotatertsi3_1_zext splitter): Ditto. 2011-08-23 Kirill Yukhin - * common/config/i386/i386-common.c (OPTION_MASK_ISA_BMI2_SET): - New. + * common/config/i386/i386-common.c (OPTION_MASK_ISA_BMI2_SET): New. (OPTION_MASK_ISA_BMI2_UNSET): Likewise. (ix86_handle_option): Handle OPT_mbmi2 case. * config.gcc (i[34567]86-*-*): Add bmi2intrin.h. @@ -93,8 +95,7 @@ PR middle-end/50161 * simplify-rtx.c (simplify_const_unary_operation): If - op is CONST_INT, don't look at op_mode, but use instead - mode. + op is CONST_INT, don't look at op_mode, but use instead mode. * optabs.c (add_equal_note): For FFS, CLZ, CTZ, CLRSB, POPCOUNT, PARITY and BSWAP use operand mode for operation and TRUNCATE/ZERO_EXTEND if needed. @@ -144,8 +145,7 @@ * tree-data-ref.c (dr_analyze_indices): Add comments, handle REALPART_EXPR and IMAGPART_EXPR similar to ARRAY_REFs. - (create_data_ref): Also dump access functions for the created - data-ref. + (create_data_ref): Also dump access functions for the created data-ref. 2011-08-22 Uros Bizjak Kirill Yukhin diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 8d3e45af600..09ee66efaf4 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -88,8 +88,11 @@ ;; We use the Y prefix to denote any number of conditional register sets: ;; z First SSE register. ;; 2 SSE2 enabled +;; 3 SSE3 enabled +;; 4 SSE4_1 enabled ;; i SSE2 inter-unit moves enabled ;; m MMX inter-unit moves enabled +;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled ;; d Integer register when integer DFmode moves are enabled ;; x Integer register when integer XFmode moves are enabled @@ -113,6 +116,10 @@ "TARGET_MMX && TARGET_INTER_UNIT_MOVES ? MMX_REGS : NO_REGS" "@internal Any MMX register, when inter-unit moves are enabled.") +(define_register_constraint "Yp" + "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" + "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.") + (define_register_constraint "Yd" "(TARGET_64BIT || (TARGET_INTEGER_DFMODE_MOVES && optimize_function_for_speed_p (cfun))) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3ce2a015e3f..e739d83f4d6 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -5650,49 +5650,11 @@ (set_attr "mode" "SI")]) (define_insn "*addhi_1" - [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") - (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") - (match_operand:HI 2 "general_operand" "rn,rm"))) + [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r,Yp") + (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r,Yp") + (match_operand:HI 2 "general_operand" "rn,rm,0,ln"))) (clobber (reg:CC FLAGS_REG))] - "TARGET_PARTIAL_REG_STALL - && ix86_binary_operator_ok (PLUS, HImode, operands)" -{ - switch (get_attr_type (insn)) - { - case TYPE_INCDEC: - if (operands[2] == const1_rtx) - return "inc{w}\t%0"; - else - { - gcc_assert (operands[2] == constm1_rtx); - return "dec{w}\t%0"; - } - - default: - if (x86_maybe_negate_const_int (&operands[2], HImode)) - return "sub{w}\t{%2, %0|%0, %2}"; - - return "add{w}\t{%2, %0|%0, %2}"; - } -} - [(set (attr "type") - (if_then_else (match_operand:HI 2 "incdec_operand" "") - (const_string "incdec") - (const_string "alu"))) - (set (attr "length_immediate") - (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) - (const_string "1") - (const_string "*"))) - (set_attr "mode" "HI")]) - -(define_insn "*addhi_1_lea" - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm,r,r") - (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r,r") - (match_operand:HI 2 "general_operand" "rmn,rn,0,ln"))) - (clobber (reg:CC FLAGS_REG))] - "!TARGET_PARTIAL_REG_STALL - && ix86_binary_operator_ok (PLUS, HImode, operands)" + "ix86_binary_operator_ok (PLUS, HImode, operands)" { switch (get_attr_type (insn)) { @@ -5739,62 +5701,15 @@ (const_string "*"))) (set_attr "mode" "HI,HI,HI,SI")]) -;; %%% Potential partial reg stall on alternative 2. What to do? -(define_insn "*addqi_1" - [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") - (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:QI 2 "general_operand" "qn,qmn,rn"))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_PARTIAL_REG_STALL - && ix86_binary_operator_ok (PLUS, QImode, operands)" -{ - int widen = (which_alternative == 2); - switch (get_attr_type (insn)) - { - case TYPE_INCDEC: - if (operands[2] == const1_rtx) - return widen ? "inc{l}\t%k0" : "inc{b}\t%0"; - else - { - gcc_assert (operands[2] == constm1_rtx); - return widen ? "dec{l}\t%k0" : "dec{b}\t%0"; - } - - default: - if (x86_maybe_negate_const_int (&operands[2], QImode)) - { - if (widen) - return "sub{l}\t{%2, %k0|%k0, %2}"; - else - return "sub{b}\t{%2, %0|%0, %2}"; - } - if (widen) - return "add{l}\t{%k2, %k0|%k0, %k2}"; - else - return "add{b}\t{%2, %0|%0, %2}"; - } -} - [(set (attr "type") - (if_then_else (match_operand:QI 2 "incdec_operand" "") - (const_string "incdec") - (const_string "alu"))) - (set (attr "length_immediate") - (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) - (const_string "1") - (const_string "*"))) - (set_attr "mode" "QI,QI,SI")]) - ;; %%% Potential partial reg stall on alternatives 3 and 4. What to do? -(define_insn "*addqi_1_lea" - [(set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,q,r,r,r") - (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,q,0,r,r") - (match_operand:QI 2 "general_operand" "qmn,qn,0,rn,0,ln"))) +(define_insn "*addqi_1" + [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,q,r,r,Yp") + (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,q,0,r,Yp") + (match_operand:QI 2 "general_operand" "qn,qm,0,rn,0,ln"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_PARTIAL_REG_STALL - && ix86_binary_operator_ok (PLUS, QImode, operands)" + "ix86_binary_operator_ok (PLUS, QImode, operands)" { - int widen = (which_alternative == 3 || which_alternative == 4); + bool widen = (which_alternative == 3 || which_alternative == 4); switch (get_attr_type (insn)) { @@ -5851,7 +5766,7 @@ (define_insn "*addqi_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) (plus:QI (match_dup 0) - (match_operand:QI 1 "general_operand" "qn,qnm"))) + (match_operand:QI 1 "general_operand" "qn,qm"))) (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && !(MEM_P (operands[0]) && MEM_P (operands[1]))" @@ -9294,53 +9209,11 @@ "operands[2] = gen_lowpart (SImode, operands[2]);") (define_insn "*ashlhi3_1" - [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") - (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "nonmemory_operand" "cI"))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_PARTIAL_REG_STALL - && ix86_binary_operator_ok (ASHIFT, HImode, operands)" -{ - switch (get_attr_type (insn)) - { - case TYPE_ALU: - gcc_assert (operands[2] == const1_rtx); - return "add{w}\t%0, %0"; - - default: - if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) - return "sal{w}\t%0"; - else - return "sal{w}\t{%2, %0|%0, %2}"; - } -} - [(set (attr "type") - (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") - (const_int 0)) - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) - (const_string "alu") - ] - (const_string "ishift"))) - (set (attr "length_immediate") - (if_then_else - (ior (eq_attr "type" "alu") - (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") - (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)") - (const_int 0))))) - (const_string "0") - (const_string "*"))) - (set_attr "mode" "HI")]) - -(define_insn "*ashlhi3_1_lea" - [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,Yp") (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,l") (match_operand:QI 2 "nonmemory_operand" "cI,M"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_PARTIAL_REG_STALL - && ix86_binary_operator_ok (ASHIFT, HImode, operands)" + "ix86_binary_operator_ok (ASHIFT, HImode, operands)" { switch (get_attr_type (insn)) { @@ -9380,68 +9253,13 @@ (const_string "*"))) (set_attr "mode" "HI,SI")]) +;; %%% Potential partial reg stall on alternative 1. What to do? (define_insn "*ashlqi3_1" - [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r") - (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "cI,cI"))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_PARTIAL_REG_STALL - && ix86_binary_operator_ok (ASHIFT, QImode, operands)" -{ - switch (get_attr_type (insn)) - { - case TYPE_ALU: - gcc_assert (operands[2] == const1_rtx); - if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1])) - return "add{l}\t%k0, %k0"; - else - return "add{b}\t%0, %0"; - - default: - if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) - { - if (get_attr_mode (insn) == MODE_SI) - return "sal{l}\t%k0"; - else - return "sal{b}\t%0"; - } - else - { - if (get_attr_mode (insn) == MODE_SI) - return "sal{l}\t{%2, %k0|%k0, %2}"; - else - return "sal{b}\t{%2, %0|%0, %2}"; - } - } -} - [(set (attr "type") - (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") - (const_int 0)) - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) - (const_string "alu") - ] - (const_string "ishift"))) - (set (attr "length_immediate") - (if_then_else - (ior (eq_attr "type" "alu") - (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") - (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)") - (const_int 0))))) - (const_string "0") - (const_string "*"))) - (set_attr "mode" "QI,SI")]) - -;; %%% Potential partial reg stall on alternative 2. What to do? -(define_insn "*ashlqi3_1_lea" - [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r") + [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,Yp") (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,l") (match_operand:QI 2 "nonmemory_operand" "cI,cI,M"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_PARTIAL_REG_STALL - && ix86_binary_operator_ok (ASHIFT, QImode, operands)" + "ix86_binary_operator_ok (ASHIFT, QImode, operands)" { switch (get_attr_type (insn)) {