Add support for MCore port

From-SVN: r31974

gcc/ChangeLog

@@ -1,3 +1,13 @@
+2000-02-14  Nick Clifton  <nickc@cygnus.com>
+
+	* configure.in: Add mcore-elf and mcore-pe targets.
+	* configure: Regenerate.
+
+	* NEWS: Add note that MCore port has been contributed.
+
+	* invoke.texi: Document command line switches for MCore port.
+	* install.texi: Add MCore to list of supported targets.
+
 2000-02-14  Geoff Keating  <geoffk@cygnus.com>
 
 	* collect2.c (main) [COLLECT_EXPORT_LIST]: If we have frames,

gcc/NEWS

@@ -6,6 +6,8 @@ Target specific NEWS
     RS6000/PowerPC: -mcpu=401 was added as an alias for -mcpu=403.  -mcpu=e603e
 		    was added to do -mcpu=603e and -msoft-float.
 
+    MCore: Port of gcc to Motorola's MCore 210 and 340 contributed.
+    
 Noteworthy changes in GCC for EGCS 1.1.
 ---------------------------------------
 

gcc/configure.in

@@ -821,6 +821,12 @@ changequote([,])dnl
 	arm*-*-elf)
 		tm_file=arm/unknown-elf.h
 		tmake_file=arm/t-arm-elf
+#		tm_file=arm2/unknown-elf.h
+#		tmake_file=arm2/t-arm-elf
+#		out_file=arm2/arm.c
+#		xm_file=arm2/xm-arm.h
+#		md_file=arm2/arm.md
+#		tm_p_file=arm2/arm-protos.h
 		;;
         arm*-*-oabi)
 		tm_file=arm/unknown-elf-oabi.h
@@ -2365,6 +2371,14 @@ changequote([,])dnl
 		xmake_file=m88k/x-sysv4
 		tmake_file=m88k/t-sysv4
 		;;
+	mcore-*-elf)
+		tm_file=mcore/mcore-elf.h
+		tmake_file=mcore/t-mcore
+		;;
+	mcore-*-pe*)
+		tm_file=mcore/mcore-pe.h
+		tmake_file=mcore/t-mcore-pe
+		;;
 	mips-sgi-irix6*)		# SGI System V.4., IRIX 6
 		if test "x$gnu_ld" = xyes
 		then

gcc/install.texi

@@ -747,7 +747,7 @@ Here are the possible CPU types:
 @c gmicro, fx80, spur and tahoe omitted since they don't work.
 1750a, a29k, alpha, arm, c@var{n}, clipper, dsp16xx, elxsi, fr30, h8300,
 hppa1.0, hppa1.1, i370, i386, i486, i586, i686, i786, i860, i960, m32r,
-m68000, m68k, m88k, mips, mipsel, mips64, mips64el, mn10200, mn10300,
+m68000, m68k, m88k, mcore, mips, mipsel, mips64, mips64el, mn10200, mn10300,
 ns32k, pdp11, powerpc, powerpcle, romp, rs6000, sh, sparc, sparclite,
 sparc64, v850, vax, we32k.
 @end quotation

gcc/invoke.texi

@@ -427,6 +427,13 @@ in the following sections.
 -m32032 -m32332 -m32532 -m32081 -m32381 -mmult-add -mnomult-add
 -msoft-float -mrtd -mnortd -mregparam -mnoregparam -msb -mnosb
 -mbitfield -mnobitfield -mhimem -mnohimem
+
+@emph{MCore Options}
+-mhardlit, -mno-hardlit -mdiv -mno-div -mrelax-immediates 
+-mno-relax-immediates -mwide-bitfields -mno-wide-bitfields
+-m4byte-functions -mno-4byte-functions -mcallgraph-data
+-mno-callgraph-data -mslow-bytes -mno-slow-bytes -mno-lsim
+-mlittle-endian -mbig-endian -m210 -m340 -mstack-increment
 @end smallexample
 
 @item Code Generation Options
@@ -3758,6 +3765,7 @@ that macro, which enables you to change the defaults.
 * TMS320C3x/C4x Options::
 * V850 Options::
 * ARC Options::
+* MCore Options::
 * NS32K Options::
 @end menu
 
@@ -6833,6 +6841,62 @@ This is the default for all platforms.
 
 @end table
 
+@node MCore Options
+@subsection MCore Options
+@cindex MCore options
+
+These are the @samp{-m} options defined for the Motorola M*Core
+processors.  
+
+@table @code
+
+@item -mhardlit
+@itemx -mhardlit
+@itemx -mno-hardlit
+Inline constants into the code stream if it can be done in two
+instructions or less.
+
+@item -mdiv
+@itemx -mdiv
+@itemx -mno-div
+Use the divide instruction.  (Enabled by default).
+
+@item -mrelax-immediate
+@itemx -mrelax-immediate
+@itemx -mno-relax-immediate
+Allow arbitary sized immediated in bit operations.
+
+@item -mwide-bitfields
+@itemx -mwide-bitfields
+@itemx -mno-wide-bitfields
+Always treat bitfields as int-sized.
+
+@item -m4byte-functions
+@itemx -m4byte-functions
+@itemx -mno-4byte-functions
+Force all functions to be aligfned to a four byte boundary.
+
+@item -mcallgraph-data
+@itemx -mcallgraph-data
+@itemx -mno-callgraph-data
+Emit callgraph information.
+
+@item -mslow-bytes
+@itemx -mslow-bytes
+@itemx -mno-slow-bytes
+Prefer word access when reading byte quantities.
+
+@item -mlittle-endian
+@itemx -mlittle-endian
+@itemx -mbig-endian
+Genreate code for a little endian target.
+
+@item -m210
+@itemx -m210
+@itemx -m340
+Generate code for the 210 processor.
+
+@end table
 
 
 @node Code Gen Options