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i386: Remove TARGET_VECTORIZE_BUILTIN_CONVERSION.

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Renaming all of the insn patterns as needed to the standard
optab forms.  Sadly, only one of the builtins is unused by
the various header files, so most of them must stay around.

        * config/i386/sse.md (floatv8siv8sf2): Rename from avx_cvtdq2ps256.
        (floatv4siv4sf2): Rename from sse2_cvtdq2ps.
        (floatunsv4siv4sf2): Rename from sse2_cvtudq2ps.
        (fix_truncv8sfv8si2): Rename from avx_cvttps2dq256.
        (fix_truncv4sfv4si2): Rename from sse2_cvttps2dq.
        (floatv4siv4df2): Rename from avx_cvtdq2pd256.
        (fix_truncv4dfv4si2): Rename from avx_cvttpd2dq256.
        (vec_unpacku_float_hi_v8si): Update for insn pattern name changes.
        * config/i386/i386.md (splitters for int-float conversion): Likewise.
        * config/i386/i386.c (ix86_split_convert_uns_si_sse): Likewise.
        (bdesc_args): Likewise.
        (enum ix86_builtins) [IX86_BUILTIN_CVTUDQ2PS]: Remove.
        (ix86_vectorize_builtin_conversion): Remove.
        (TARGET_VECTORIZE_BUILTIN_CONVERSION): Remove.

From-SVN: r180709
This commit is contained in:
Richard Henderson 2011-10-31 12:36:57 -07:00 • committed by Richard Henderson
parent 1fb80b0c53
commit 788a290865
4 changed files with 48 additions and 119 deletions
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17
gcc/ChangeLog
View file

@ -1,3 +1,20 @@
2011-10-31 Richard Henderson <rth@redhat.com>
* config/i386/sse.md (floatv8siv8sf2): Rename from avx_cvtdq2ps256.
(floatv4siv4sf2): Rename from sse2_cvtdq2ps.
(floatunsv4siv4sf2): Rename from sse2_cvtudq2ps.
(fix_truncv8sfv8si2): Rename from avx_cvttps2dq256.
(fix_truncv4sfv4si2): Rename from sse2_cvttps2dq.
(floatv4siv4df2): Rename from avx_cvtdq2pd256.
(fix_truncv4dfv4si2): Rename from avx_cvttpd2dq256.
(vec_unpacku_float_hi_v8si): Update for insn pattern name changes.
* config/i386/i386.md (splitters for int-float conversion): Likewise.
* config/i386/i386.c (ix86_split_convert_uns_si_sse): Likewise.
(bdesc_args): Likewise.
(enum ix86_builtins) [IX86_BUILTIN_CVTUDQ2PS]: Remove.
(ix86_vectorize_builtin_conversion): Remove.
(TARGET_VECTORIZE_BUILTIN_CONVERSION): Remove.
2011-10-31 Martin Jambor <mjambor@suse.cz>
* ipa-prop.c (mark_modified): Moved up in the file.

110
gcc/config/i386/i386.c
View file

@ -16857,7 +16857,7 @@ ix86_split_convert_uns_si_sse (rtx operands[])
x = gen_rtx_REG (V4SImode, REGNO (value));
if (vecmode == V4SFmode)
emit_insn (gen_sse2_cvttps2dq (x, value));
emit_insn (gen_fix_truncv4sfv4si2 (x, value));
else
emit_insn (gen_sse2_cvttpd2dq (x, value));
value = x;
@ -25077,8 +25077,6 @@ enum ix86_builtins
IX86_BUILTIN_CPYSGNPS256,
IX86_BUILTIN_CPYSGNPD256,
IX86_BUILTIN_CVTUDQ2PS,
/* FMA4 instructions. */
IX86_BUILTIN_VFMADDSS,
IX86_BUILTIN_VFMADDSD,
@ -25791,8 +25789,7 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
@ -25809,7 +25806,7 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
@ -26147,14 +26144,14 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
{ OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
{ OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
{ OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
{ OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
@ -29406,96 +29403,6 @@ ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
return new_fndecl;
}
/* Returns a decl of a function that implements conversion of an integer vector
into a floating-point vector, or vice-versa. DEST_TYPE and SRC_TYPE
are the types involved when converting according to CODE.
Return NULL_TREE if it is not available. */
static tree
ix86_vectorize_builtin_conversion (unsigned int code,
tree dest_type, tree src_type)
{
if (! TARGET_SSE2)
return NULL_TREE;
switch (code)
{
case FLOAT_EXPR:
switch (TYPE_MODE (src_type))
{
case V4SImode:
switch (TYPE_MODE (dest_type))
{
case V4SFmode:
return (TYPE_UNSIGNED (src_type)
? ix86_builtins[IX86_BUILTIN_CVTUDQ2PS]
: ix86_builtins[IX86_BUILTIN_CVTDQ2PS]);
case V4DFmode:
return (TYPE_UNSIGNED (src_type)
? NULL_TREE
: ix86_builtins[IX86_BUILTIN_CVTDQ2PD256]);
default:
return NULL_TREE;
}
break;
case V8SImode:
switch (TYPE_MODE (dest_type))
{
case V8SFmode:
return (TYPE_UNSIGNED (src_type)
? NULL_TREE
: ix86_builtins[IX86_BUILTIN_CVTDQ2PS256]);
default:
return NULL_TREE;
}
break;
default:
return NULL_TREE;
}
case FIX_TRUNC_EXPR:
switch (TYPE_MODE (dest_type))
{
case V4SImode:
switch (TYPE_MODE (src_type))
{
case V4SFmode:
return (TYPE_UNSIGNED (dest_type)
? NULL_TREE
: ix86_builtins[IX86_BUILTIN_CVTTPS2DQ]);
case V4DFmode:
return (TYPE_UNSIGNED (dest_type)
? NULL_TREE
: ix86_builtins[IX86_BUILTIN_CVTTPD2DQ256]);
default:
return NULL_TREE;
}
break;
case V8SImode:
switch (TYPE_MODE (src_type))
{
case V8SFmode:
return (TYPE_UNSIGNED (dest_type)
? NULL_TREE
: ix86_builtins[IX86_BUILTIN_CVTTPS2DQ256]);
default:
return NULL_TREE;
}
break;
default:
return NULL_TREE;
}
default:
return NULL_TREE;
}
return NULL_TREE;
}
/* Returns a code for a target-specific builtin that implements
reciprocal of the function, or NULL_TREE if not available. */
@ -37695,9 +37602,6 @@ ix86_autovectorize_vector_sizes (void)
#define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
ix86_builtin_vectorized_function
#undef TARGET_VECTORIZE_BUILTIN_CONVERSION
#define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
#undef TARGET_BUILTIN_RECIPROCAL
#define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal

24
gcc/config/i386/i386.md
View file

@ -5053,8 +5053,10 @@
emit_insn (gen_sse2_loadld (operands[4],
CONST0_RTX (V4SImode), operands[2]));
}
emit_insn
(gen_sse2_cvtdq2<ssevecmodesuffix> (operands[3], operands[4]));
if (<ssevecmode>mode == V4SImode)
emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
else
emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
DONE;
})
@ -5076,8 +5078,10 @@
emit_insn (gen_sse2_loadld (operands[4],
CONST0_RTX (V4SImode), operands[1]));
emit_insn
(gen_sse2_cvtdq2<ssevecmodesuffix> (operands[3], operands[4]));
if (<ssevecmode>mode == V4SFmode)
emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
else
emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
DONE;
})
@ -5120,8 +5124,10 @@
operands[4] = simplify_gen_subreg (V4SImode, operands[1], SImode, 0);
else
gcc_unreachable ();
emit_insn
(gen_sse2_cvtdq2<ssevecmodesuffix> (operands[3], operands[4]));
if (<ssevecmode>mode == V4SFmode)
emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
else
emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
DONE;
})
@ -5142,8 +5148,10 @@
emit_insn (gen_sse2_loadld (operands[4],
CONST0_RTX (V4SImode), operands[1]));
emit_insn
(gen_sse2_cvtdq2<ssevecmodesuffix> (operands[3], operands[4]));
if (<ssevecmode>mode == V4SFmode)
emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
else
emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
DONE;
})

16
gcc/config/i386/sse.md
View file

@ -2224,7 +2224,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")])
(define_insn "avx_cvtdq2ps256"
(define_insn "floatv8siv8sf2"
[(set (match_operand:V8SF 0 "register_operand" "=x")
(float:V8SF (match_operand:V8SI 1 "nonimmediate_operand" "xm")))]
"TARGET_AVX"
@ -2233,7 +2233,7 @@
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
(define_insn "sse2_cvtdq2ps"
(define_insn "floatv4siv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
@ -2242,7 +2242,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V4SF")])
(define_expand "sse2_cvtudq2ps"
(define_expand "floatunsv4siv4sf2"
[(set (match_dup 5)
(float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "")))
(set (match_dup 6)
@ -2293,7 +2293,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "avx_cvttps2dq256"
(define_insn "fix_truncv8sfv8si2"
[(set (match_operand:V8SI 0 "register_operand" "=x")
(fix:V8SI (match_operand:V8SF 1 "nonimmediate_operand" "xm")))]
"TARGET_AVX"
@ -2302,7 +2302,7 @@
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
(define_insn "sse2_cvttps2dq"
(define_insn "fix_truncv4sfv4si2"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
@ -2495,7 +2495,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")])
(define_insn "avx_cvtdq2pd256"
(define_insn "floatv4siv4df2"
[(set (match_operand:V4DF 0 "register_operand" "=x")
(float:V4DF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
"TARGET_AVX"
@ -2591,7 +2591,7 @@
(set_attr "athlon_decode" "vector")
(set_attr "bdver1_decode" "double")])
(define_insn "avx_cvttpd2dq256"
(define_insn "fix_truncv4dfv4si2"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
"TARGET_AVX"
@ -2995,7 +2995,7 @@
for (i = 2; i < 5; i++)
tmp[i] = gen_reg_rtx (V4DFmode);
emit_insn (gen_vec_extract_hi_v8si (tmp[5], operands[1]));
emit_insn (gen_avx_cvtdq2pd256 (tmp[2], tmp[5]));
emit_insn (gen_floatv4siv4df2 (tmp[2], tmp[5]));
emit_insn (gen_rtx_SET (VOIDmode, tmp[3],
gen_rtx_LT (V4DFmode, tmp[2], tmp[0])));
emit_insn (gen_andv4df3 (tmp[4], tmp[3], tmp[1]));