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[PATCH 3/5][Arm] New pattern for CSINC instructions

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This patch adds a new pattern, *thumb2_csinc, for generating CSINC
instructions. It also modifies an existing pattern, *thumb2_cond_arith, to
output CINC when the operation is an addition and TARGET_COND_ARITH is true.

gcc/ChangeLog:

	* config/arm/thumb2.md (*thumb2_csinc): New.
	(*thumb2_cond_arith): Generate CINC where possible.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/csinc-1.c: New test.

Co-authored-by: Omar Tahir <omar.tahir@arm.com>
This commit is contained in:
Sudi Das 2020-09-18 16:30:11 +01:00 • committed by Omar Tahir
parent c2bb84be4a
commit 778f19ff95
2 changed files with 42 additions and 0 deletions
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19
gcc/config/arm/thumb2.md
View file

@ -744,6 +744,10 @@
return \"%i5\\t%0, %1, %2, lsr #31\";
output_asm_insn (\"cmp\\t%2, %3\", operands);
if (GET_CODE (operands[5]) == PLUS && TARGET_COND_ARITH)
return \"cinc\\t%0, %1, %d4\";
if (GET_CODE (operands[5]) == AND)
{
output_asm_insn (\"ite\\t%D4\", operands);
@ -952,6 +956,21 @@
(set_attr "predicable" "no")]
)
(define_insn "*thumb2_csinc"
[(set (match_operand:SI 0 "arm_general_register_operand" "=r, r")
(if_then_else:SI
(match_operand 1 "arm_comparison_operation" "")
(plus:SI (match_operand:SI 2 "arm_general_register_operand" "r, r")
(const_int 1))
(match_operand:SI 3 "reg_or_zero_operand" "r, Pz")))]
"TARGET_COND_ARITH"
"@
csinc\\t%0, %3, %2, %D1
csinc\\t%0, zr, %2, %D1"
[(set_attr "type" "csel")
(set_attr "predicable" "no")]
)
(define_insn "*thumb2_movcond"
[(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts")
(if_then_else:SI

23
gcc/testsuite/gcc.target/arm/csinc-1.c Normal file
View file

@ -0,0 +1,23 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
/* { dg-options "-O2 -march=armv8.1-m.main" } */
int
test_csinc32_condasn1(int w0, int w1, int w2, int w3)
{
int w4;
/* { dg-final { scan-assembler "csinc\tr\[0-9\]*.*ne" } } */
w4 = (w0 == w1) ? (w2 + 1) : w3;
return w4;
}
int
test_csinc32_condasn2(int w0, int w1, int w2, int w3)
{
int w4;
/* { dg-final { scan-assembler "csinc\tr\[0-9\]*.*eq" } } */
w4 = (w0 == w1) ? w3 : (w2 + 1);
return w4;
}