sse.md (vec_set<mode>_0): Use sse4_noavx isa instead of sse4 for the first alternative...
* config/i386/sse.md (vec_set<mode>_0): Use sse4_noavx isa instead of sse4 for the first alternative, drop %v from the template and d operand modifier. Split second alternative into one sse4_noavx and one avx alternative, use *x instead of *v in the former and v instead of *v in the latter. (*sse4_1_extractps): Use noavx isa instead of * for the first alternative, drop %v from the template. Split second alternative into one noavx and one avx alternative, use *x instead of *v in the former and v instead of *v in the latter. (<vi8_sse4_1_avx2_avx512>_movntdqa): Guard the first 2 alternatives with noavx and the last one with avx. (sse4_1_phminposuw): Guard first alternative with noavx isa, split the second one into one noavx and one avx alternative, use *x and Bm in the former and x and m in the latter one. (<sse4_1>_ptest<mode>): Use noavx instead of * for the first two alternatives. From-SVN: r236660
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
520c86db4c
commit
7733939d25
2 changed files with 56 additions and 35 deletions
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@ -1,5 +1,22 @@
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2016-05-24 Jakub Jelinek <jakub@redhat.com>
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* config/i386/sse.md (vec_set<mode>_0): Use sse4_noavx isa instead
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of sse4 for the first alternative, drop %v from the template
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and d operand modifier. Split second alternative into one sse4_noavx
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and one avx alternative, use *x instead of *v in the former and v
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instead of *v in the latter.
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(*sse4_1_extractps): Use noavx isa instead of * for the first
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alternative, drop %v from the template. Split second alternative into
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one noavx and one avx alternative, use *x instead of *v in the
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former and v instead of *v in the latter.
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(<vi8_sse4_1_avx2_avx512>_movntdqa): Guard the first 2 alternatives
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with noavx and the last one with avx.
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(sse4_1_phminposuw): Guard first alternative with noavx isa,
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split the second one into one noavx and one avx alternative,
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use *x and Bm in the former and x and m in the latter one.
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(<sse4_1>_ptest<mode>): Use noavx instead of * for the first two
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alternatives.
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* config/i386/sse.md (sse4_1_<code>v8qiv8hi2<mask_name>): Limit
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first two alternatives to noavx, use *x instead of *v in the second
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one, add avx alternative without *.
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@ -6623,18 +6623,19 @@
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;; see comment above inline_secondary_memory_needed function in i386.c
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(define_insn "vec_set<mode>_0"
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[(set (match_operand:VI4F_128 0 "nonimmediate_operand"
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"=Yr,*v,v,Yi,x,x,v,Yr ,*x ,x ,m ,m ,m")
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"=Yr,*x,v,v,Yi,x,x,v,Yr ,*x ,x ,m ,m ,m")
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(vec_merge:VI4F_128
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(vec_duplicate:VI4F_128
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(match_operand:<ssescalarmode> 2 "general_operand"
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" Yr,*v,m,r ,m,x,v,*rm,*rm,*rm,!x,!*re,!*fF"))
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" Yr,*x,v,m,r ,m,x,v,*rm,*rm,*rm,!x,!*re,!*fF"))
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(match_operand:VI4F_128 1 "vector_move_operand"
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" C , C,C,C ,C,0,v,0 ,0 ,x ,0 ,0 ,0")
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" C , C,C,C,C ,C,0,v,0 ,0 ,x ,0 ,0 ,0")
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(const_int 1)))]
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"TARGET_SSE"
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"@
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%vinsertps\t{$0xe, %d2, %0|%0, %d2, 0xe}
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%vinsertps\t{$0xe, %d2, %0|%0, %d2, 0xe}
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insertps\t{$0xe, %2, %0|%0, %2, 0xe}
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insertps\t{$0xe, %2, %0|%0, %2, 0xe}
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vinsertps\t{$0xe, %2, %2, %0|%0, %2, %2, 0xe}
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%vmov<ssescalarmodesuffix>\t{%2, %0|%0, %2}
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%vmovd\t{%2, %0|%0, %2}
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movss\t{%2, %0|%0, %2}
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@ -6646,20 +6647,20 @@
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#
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#
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#"
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[(set_attr "isa" "sse4,sse4,sse2,sse2,noavx,noavx,avx,sse4_noavx,sse4_noavx,avx,*,*,*")
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[(set_attr "isa" "sse4_noavx,sse4_noavx,avx,sse2,sse2,noavx,noavx,avx,sse4_noavx,sse4_noavx,avx,*,*,*")
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(set (attr "type")
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(cond [(eq_attr "alternative" "0,1,7,8,9")
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(cond [(eq_attr "alternative" "0,1,2,8,9,10")
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(const_string "sselog")
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(eq_attr "alternative" "11")
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(const_string "imov")
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(eq_attr "alternative" "12")
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(const_string "imov")
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(eq_attr "alternative" "13")
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(const_string "fmov")
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]
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(const_string "ssemov")))
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(set_attr "prefix_extra" "*,*,*,*,*,*,*,1,1,1,*,*,*")
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(set_attr "length_immediate" "*,*,*,*,*,*,*,1,1,1,*,*,*")
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(set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,maybe_vex,orig,orig,vex,orig,orig,vex,*,*,*")
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(set_attr "mode" "SF,SF,<ssescalarmode>,SI,SF,SF,SF,TI,TI,TI,*,*,*")])
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(set_attr "prefix_extra" "*,*,*,*,*,*,*,*,1,1,1,*,*,*")
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(set_attr "length_immediate" "*,*,*,*,*,*,*,*,1,1,1,*,*,*")
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(set_attr "prefix" "orig,orig,maybe_evex,maybe_vex,maybe_vex,orig,orig,vex,orig,orig,vex,*,*,*")
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(set_attr "mode" "SF,SF,SF,<ssescalarmode>,SI,SF,SF,SF,TI,TI,TI,*,*,*")])
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;; A subset is vec_setv4sf.
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(define_insn "*vec_setv4sf_sse4_1"
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@ -6761,14 +6762,15 @@
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"operands[1] = gen_lowpart (SFmode, operands[1]);")
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(define_insn_and_split "*sse4_1_extractps"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=rm,rm,v,v")
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[(set (match_operand:SF 0 "nonimmediate_operand" "=rm,rm,rm,v,v")
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(vec_select:SF
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(match_operand:V4SF 1 "register_operand" "Yr,*v,0,v")
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(parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n,n")])))]
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(match_operand:V4SF 1 "register_operand" "Yr,*x,v,0,v")
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(parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n,n,n")])))]
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"TARGET_SSE4_1"
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"@
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%vextractps\t{%2, %1, %0|%0, %1, %2}
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%vextractps\t{%2, %1, %0|%0, %1, %2}
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extractps\t{%2, %1, %0|%0, %1, %2}
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extractps\t{%2, %1, %0|%0, %1, %2}
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vextractps\t{%2, %1, %0|%0, %1, %2}
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#
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#"
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"&& reload_completed && SSE_REG_P (operands[0])"
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@ -6793,13 +6795,13 @@
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}
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DONE;
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}
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[(set_attr "isa" "*,*,noavx,avx")
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(set_attr "type" "sselog,sselog,*,*")
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(set_attr "prefix_data16" "1,1,*,*")
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(set_attr "prefix_extra" "1,1,*,*")
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(set_attr "length_immediate" "1,1,*,*")
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(set_attr "prefix" "maybe_vex,maybe_vex,*,*")
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(set_attr "mode" "V4SF,V4SF,*,*")])
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[(set_attr "isa" "noavx,noavx,avx,noavx,avx")
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(set_attr "type" "sselog,sselog,sselog,*,*")
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(set_attr "prefix_data16" "1,1,1,*,*")
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(set_attr "prefix_extra" "1,1,1,*,*")
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(set_attr "length_immediate" "1,1,1,*,*")
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(set_attr "prefix" "orig,orig,maybe_evex,*,*")
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(set_attr "mode" "V4SF,V4SF,V4SF,*,*")])
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(define_insn_and_split "*vec_extractv4sf_mem"
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[(set (match_operand:SF 0 "register_operand" "=v,*r,f")
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@ -14582,14 +14584,15 @@
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[(V2DI "sse4_1") (V4DI "avx2") (V8DI "avx512f")])
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(define_insn "<vi8_sse4_1_avx2_avx512>_movntdqa"
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[(set (match_operand:VI8_AVX2_AVX512F 0 "register_operand" "=Yr,*x, v")
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(unspec:VI8_AVX2_AVX512F [(match_operand:VI8_AVX2_AVX512F 1 "memory_operand" "m, m, m")]
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[(set (match_operand:VI8_AVX2_AVX512F 0 "register_operand" "=Yr,*x,v")
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(unspec:VI8_AVX2_AVX512F [(match_operand:VI8_AVX2_AVX512F 1 "memory_operand" "m,m,m")]
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UNSPEC_MOVNTDQA))]
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"TARGET_SSE4_1"
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"%vmovntdqa\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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[(set_attr "isa" "noavx,noavx,avx")
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(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1,1,*")
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(set_attr "prefix" "maybe_vex,maybe_vex,evex")
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(set_attr "prefix" "orig,orig,maybe_evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "<sse4_1_avx2>_mpsadbw"
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@ -14715,14 +14718,15 @@
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "sse4_1_phminposuw"
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[(set (match_operand:V8HI 0 "register_operand" "=Yr,*x")
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(unspec:V8HI [(match_operand:V8HI 1 "vector_operand" "YrBm,*xBm")]
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[(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,x")
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(unspec:V8HI [(match_operand:V8HI 1 "vector_operand" "YrBm,*xBm,xm")]
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UNSPEC_PHMINPOSUW))]
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"TARGET_SSE4_1"
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"%vphminposuw\t{%1, %0|%0, %1}"
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[(set_attr "type" "sselog1")
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[(set_attr "isa" "noavx,noavx,avx")
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(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "prefix" "orig,orig,vex")
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(set_attr "mode" "TI")])
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(define_insn "avx2_<code>v16qiv16hi2<mask_name>"
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@ -14980,10 +14984,10 @@
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UNSPEC_PTEST))]
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"TARGET_SSE4_1"
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"%vptest\t{%1, %0|%0, %1}"
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[(set_attr "isa" "*,*,avx")
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[(set_attr "isa" "noavx,noavx,avx")
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(set_attr "type" "ssecomi")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "prefix" "orig,orig,vex")
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(set (attr "btver2_decode")
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(if_then_else
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(match_test "<sseinsnmode>mode==OImode")
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