LoongArch: Fix ICE and use simplify_gen_subreg instead of gen_rtx_SUBREG directly.
loongarch_expand_vec_cond_mask_expr generates 'subreg's of 'subreg's, which are not supported
in gcc, it causes an ICE:
ice.c:55:1: error: unrecognizable insn:
55 | }
| ^
(insn 63 62 64 8 (set (reg:V4DI 278)
(subreg:V4DI (subreg:V4DF (reg:V4DI 273 [ vect__53.26 ]) 0) 0)) -1
(nil))
during RTL pass: vregs
ice.c:55:1: internal compiler error: in extract_insn, at recog.cc:2804
Last time, Ruoyao has fixed a similar ICE:
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636156.html
This patch fixes ICE and use simplify_gen_subreg instead of gen_rtx_SUBREG as much as possible
to avoid the same ice happening again.
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_try_expand_lsx_vshuf_const): Use
simplify_gen_subreg instead of gen_rtx_SUBREG.
(loongarch_expand_vec_perm_const_2): Ditto.
(loongarch_expand_vec_cond_expr): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/pr112476-3.c: New test.
* gcc.target/loongarch/pr112476-4.c: New test.
This commit is contained in:
Jiahao Xu
Lulu Cheng
parent
40366b89e9
commit
75f9c2ea29
3 changed files with 108 additions and 33 deletions
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@ -8826,13 +8826,13 @@ loongarch_try_expand_lsx_vshuf_const (struct expand_vec_perm_d *d)
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if (d->vmode == E_V2DFmode)
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{
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sel = gen_rtx_CONST_VECTOR (E_V2DImode, gen_rtvec_v (d->nelt, rperm));
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tmp = gen_rtx_SUBREG (E_V2DImode, d->target, 0);
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tmp = simplify_gen_subreg (E_V2DImode, d->target, d->vmode, 0);
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emit_move_insn (tmp, sel);
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}
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else if (d->vmode == E_V4SFmode)
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{
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sel = gen_rtx_CONST_VECTOR (E_V4SImode, gen_rtvec_v (d->nelt, rperm));
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tmp = gen_rtx_SUBREG (E_V4SImode, d->target, 0);
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tmp = simplify_gen_subreg (E_V4SImode, d->target, d->vmode, 0);
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emit_move_insn (tmp, sel);
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}
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else
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@ -9616,8 +9616,8 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d)
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/* Adjust op1 for selecting correct value in high 128bit of target
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register.
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op1: E_V4DImode, { 4, 5, 6, 7 } -> { 2, 3, 4, 5 }. */
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rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0);
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rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, d->op0, 0);
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rtx conv_op1 = simplify_gen_subreg (E_V4DImode, op1_alt, d->vmode, 0);
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rtx conv_op0 = simplify_gen_subreg (E_V4DImode, d->op0, d->vmode, 0);
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emit_insn (gen_lasx_xvpermi_q_v4di (conv_op1, conv_op1,
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conv_op0, GEN_INT (0x21)));
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@ -9646,8 +9646,8 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d)
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emit_move_insn (op0_alt, d->op0);
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/* Generate subreg for fitting into insn gen function. */
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rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0);
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rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0);
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rtx conv_op1 = simplify_gen_subreg (E_V4DImode, op1_alt, d->vmode, 0);
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rtx conv_op0 = simplify_gen_subreg (E_V4DImode, op0_alt, d->vmode, 0);
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/* Adjust op value in temp register.
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op0 = {0,1,2,3}, op1 = {4,5,0,1} */
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@ -9693,9 +9693,10 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d)
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emit_move_insn (op1_alt, d->op1);
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emit_move_insn (op0_alt, d->op0);
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rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0);
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rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0);
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rtx conv_target = gen_rtx_SUBREG (E_V4DImode, d->target, 0);
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rtx conv_op1 = simplify_gen_subreg (E_V4DImode, op1_alt, d->vmode, 0);
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rtx conv_op0 = simplify_gen_subreg (E_V4DImode, op0_alt, d->vmode, 0);
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rtx conv_target = simplify_gen_subreg (E_V4DImode, d->target,
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d->vmode, 0);
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emit_insn (gen_lasx_xvpermi_q_v4di (conv_op1, conv_op1,
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conv_op0, GEN_INT (0x02)));
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@ -9727,9 +9728,10 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d)
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Selector sample: E_V4DImode, { 0, 1, 4 ,5 } */
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if (!d->testing_p)
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{
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rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, d->op1, 0);
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rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, d->op0, 0);
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rtx conv_target = gen_rtx_SUBREG (E_V4DImode, d->target, 0);
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rtx conv_op1 = simplify_gen_subreg (E_V4DImode, d->op1, d->vmode, 0);
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rtx conv_op0 = simplify_gen_subreg (E_V4DImode, d->op0, d->vmode, 0);
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rtx conv_target = simplify_gen_subreg (E_V4DImode, d->target,
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d->vmode, 0);
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/* We can achieve the expectation by using sinple xvpermi.q insn. */
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emit_move_insn (conv_target, conv_op1);
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@ -9754,8 +9756,8 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d)
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emit_move_insn (op1_alt, d->op1);
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emit_move_insn (op0_alt, d->op0);
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rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0);
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rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0);
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rtx conv_op1 = simplify_gen_subreg (E_V4DImode, op1_alt, d->vmode, 0);
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rtx conv_op0 = simplify_gen_subreg (E_V4DImode, op0_alt, d->vmode, 0);
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/* Adjust op value in temp regiter.
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op0 = { 0, 1, 2, 3 }, op1 = { 6, 7, 2, 3 } */
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emit_insn (gen_lasx_xvpermi_q_v4di (conv_op1, conv_op1,
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@ -9799,9 +9801,10 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d)
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emit_move_insn (op1_alt, d->op1);
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emit_move_insn (op0_alt, d->op0);
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rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0);
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rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0);
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rtx conv_target = gen_rtx_SUBREG (E_V4DImode, d->target, 0);
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rtx conv_op1 = simplify_gen_subreg (E_V4DImode, op1_alt, d->vmode, 0);
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rtx conv_op0 = simplify_gen_subreg (E_V4DImode, op0_alt, d->vmode, 0);
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rtx conv_target = simplify_gen_subreg (E_V4DImode, d->target,
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d->vmode, 0);
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emit_insn (gen_lasx_xvpermi_q_v4di (conv_op1, conv_op1,
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conv_op0, GEN_INT (0x13)));
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@ -9833,10 +9836,11 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d)
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Selector sample:E_V8SImode, { 2, 2, 2, 2, 2, 2, 2, 2 } */
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if (!d->testing_p)
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{
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rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, d->op1, 0);
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rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, d->op0, 0);
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rtx conv_op1 = simplify_gen_subreg (E_V4DImode, d->op1, d->vmode, 0);
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rtx conv_op0 = simplify_gen_subreg (E_V4DImode, d->op0, d->vmode, 0);
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rtx temp_reg = gen_reg_rtx (d->vmode);
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rtx conv_temp = gen_rtx_SUBREG (E_V4DImode, temp_reg, 0);
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rtx conv_temp = simplify_gen_subreg (E_V4DImode, temp_reg,
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d->vmode, 0);
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emit_move_insn (temp_reg, d->op0);
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@ -9945,9 +9949,11 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d)
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emit_move_insn (op0_alt, d->op0);
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emit_move_insn (op1_alt, d->op1);
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rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, d->op0, 0);
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rtx conv_op0a = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0);
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rtx conv_op1a = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0);
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rtx conv_op0 = simplify_gen_subreg (E_V4DImode, d->op0, d->vmode, 0);
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rtx conv_op0a = simplify_gen_subreg (E_V4DImode, op0_alt,
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d->vmode, 0);
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rtx conv_op1a = simplify_gen_subreg (E_V4DImode, op1_alt,
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d->vmode, 0);
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/* Duplicate op0's low 128bit in op0, then duplicate high 128bit
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in op1. After this, xvshuf.* insn's selector argument can
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@ -9980,10 +9986,12 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d)
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emit_move_insn (op0_alt, d->op0);
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emit_move_insn (op1_alt, d->op1);
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rtx conv_op0a = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0);
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rtx conv_op1a = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0);
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rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, d->op0, 0);
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rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, d->op1, 0);
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rtx conv_op0a = simplify_gen_subreg (E_V4DImode, op0_alt,
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d->vmode, 0);
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rtx conv_op1a = simplify_gen_subreg (E_V4DImode, op1_alt,
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d->vmode, 0);
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rtx conv_op0 = simplify_gen_subreg (E_V4DImode, d->op0, d->vmode, 0);
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rtx conv_op1 = simplify_gen_subreg (E_V4DImode, d->op1, d->vmode, 0);
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/* Reorganize op0's hi/lo 128bit and op1's hi/lo 128bit, to make sure
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that selector's low 128bit can access all op0's elements, and
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@ -10103,12 +10111,12 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d)
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{
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case E_V4DFmode:
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sel = gen_rtx_CONST_VECTOR (E_V4DImode, gen_rtvec_v (d->nelt, rperm));
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tmp = gen_rtx_SUBREG (E_V4DImode, d->target, 0);
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tmp = simplify_gen_subreg (E_V4DImode, d->target, d->vmode, 0);
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emit_move_insn (tmp, sel);
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break;
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case E_V8SFmode:
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sel = gen_rtx_CONST_VECTOR (E_V8SImode, gen_rtvec_v (d->nelt, rperm));
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tmp = gen_rtx_SUBREG (E_V8SImode, d->target, 0);
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tmp = simplify_gen_subreg (E_V8SImode, d->target, d->vmode, 0);
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emit_move_insn (tmp, sel);
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break;
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default:
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@ -10194,7 +10202,7 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d)
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64bit in target vector register. */
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else if (extract_ev_od)
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{
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rtx converted = gen_rtx_SUBREG (E_V4DImode, d->target, 0);
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rtx converted = simplify_gen_subreg (E_V4DImode, d->target, d->vmode, 0);
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emit_insn (gen_lasx_xvpermi_d_v4di (converted, converted,
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GEN_INT (0xD8)));
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}
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@ -11284,7 +11292,9 @@ loongarch_expand_vec_cond_expr (machine_mode mode, machine_mode vimode,
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if (mode != vimode)
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{
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xop1 = gen_reg_rtx (vimode);
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emit_move_insn (xop1, gen_rtx_SUBREG (vimode, operands[1], 0));
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emit_move_insn (xop1,
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simplify_gen_subreg (vimode, operands[1],
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mode, 0));
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}
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emit_move_insn (src1, xop1);
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}
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@ -11301,7 +11311,9 @@ loongarch_expand_vec_cond_expr (machine_mode mode, machine_mode vimode,
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if (mode != vimode)
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{
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xop2 = gen_reg_rtx (vimode);
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emit_move_insn (xop2, gen_rtx_SUBREG (vimode, operands[2], 0));
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emit_move_insn (xop2,
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simplify_gen_subreg (vimode, operands[2],
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mode, 0));
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}
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emit_move_insn (src2, xop2);
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}
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@ -11320,7 +11332,8 @@ loongarch_expand_vec_cond_expr (machine_mode mode, machine_mode vimode,
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gen_rtx_AND (vimode, mask, src1));
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/* The result is placed back to a register with the mask. */
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emit_insn (gen_rtx_SET (mask, bsel));
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emit_move_insn (operands[0], gen_rtx_SUBREG (mode, mask, 0));
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emit_move_insn (operands[0],
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simplify_gen_subreg (mode, mask, vimode, 0));
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}
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}
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58
gcc/testsuite/gcc.target/loongarch/pr112476-3.c
Normal file
58
gcc/testsuite/gcc.target/loongarch/pr112476-3.c
Normal file
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@ -0,0 +1,58 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -mlsx" } */
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#include <stdint.h>
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typedef int8_t orc_int8;
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typedef int16_t orc_int16;
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typedef int32_t orc_int32;
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typedef int64_t orc_int64;
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typedef union
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{
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orc_int32 i;
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float f;
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orc_int16 x2[2];
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orc_int8 x4[4];
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} orc_union32;
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typedef union
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{
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orc_int64 i;
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double f;
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orc_int32 x2[2];
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float x2f[2];
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orc_int16 x4[4];
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} orc_union64;
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void
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audio_orc_s32_to_double (double * restrict d1,
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const signed int * restrict s1, int n)
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{
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int i;
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orc_union64 *restrict ptr0;
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const orc_union32 *restrict ptr4;
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orc_union32 var33;
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orc_union64 var34;
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orc_union64 var35;
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orc_union64 var36;
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ptr0 = (orc_union64 *) d1;
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ptr4 = (orc_union32 *) s1;
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var34.i = 0x41e0000000000000UL;
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for (i = 0; i < n; i++) {
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var33 = ptr4[i];
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var36.f = var33.i;
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{
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orc_union64 _src1;
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orc_union64 _src2;
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orc_union64 _dest1;
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_src1.i = ((var36.i) & ((((var36.i)&0x7ff0000000000000UL) == 0) ? 0xfff0000000000000UL : 0xffffffffffffffffUL));
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_src2.i = ((var34.i) & ((((var34.i)&0x7ff0000000000000UL) == 0) ? 0xfff0000000000000UL : 0xffffffffffffffffUL));
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_dest1.f = _src1.f / _src2.f;
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var35.i = ((_dest1.i) & ((((_dest1.i)&0x7ff0000000000000UL) == 0) ? 0xfff0000000000000UL : 0xffffffffffffffffUL));
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}
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ptr0[i] = var35;
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}
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}
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4
gcc/testsuite/gcc.target/loongarch/pr112476-4.c
Normal file
4
gcc/testsuite/gcc.target/loongarch/pr112476-4.c
Normal file
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@ -0,0 +1,4 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -mlasx" } */
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#include "pr112476-3.c"
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