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xtensa: constantsynth: Add new 3-insns synthesis pattern

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This patch adds a new 3-instructions constant synthesis pattern:

- A value that can fit into a signed 12-bit after a number of either bitwise
  left or right rotations:
    => "MOVI(.N) Ax, simm12" + "SSAI (1 ... 11) or (21 ... 31)"
	+ "SRC Ax, Ax, Ax"

gcc/ChangeLog:

	* config/xtensa/xtensa.cc (xtensa_constantsynth):
	Add new pattern for the abovementioned case.

gcc/testsuite/ChangeLog:

	* gcc.target/xtensa/constsynth_3insns.c (test_4):
	Add new test function.
This commit is contained in:
Takayuki 'January June' Suwa 2022-09-10 18:29:45 +09:00 • committed by Max Filippov
parent 16d752a514
commit 75e5cc9c3a
2 changed files with 42 additions and 0 deletions
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31
gcc/config/xtensa/xtensa.cc
View file

@ -1142,6 +1142,37 @@ xtensa_constantsynth (rtx dst, HOST_WIDE_INT srcval)
xtensa_constantsynth_rtx_ADDSUBX,
divisor))
return 1;
/* loading simm12 followed by left/right bitwise rotation:
MOVI + SSAI + SRC. */
if ((srcval & 0x001FF800) == 0
|| (srcval & 0x001FF800) == 0x001FF800)
{
int32_t v;
for (shift = 1; shift < 12; ++shift)
{
v = (int32_t)(((uint32_t)srcval >> shift)
| ((uint32_t)srcval << (32 - shift)));
if (xtensa_simm12b(v))
{
emit_move_insn (dst, GEN_INT (v));
emit_insn (gen_rotlsi3 (dst, dst, GEN_INT (shift)));
return 1;
}
}
for (shift = 1; shift < 12; ++shift)
{
v = (int32_t)(((uint32_t)srcval << shift)
| ((uint32_t)srcval >> (32 - shift)));
if (xtensa_simm12b(v))
{
emit_move_insn (dst, GEN_INT (v));
emit_insn (gen_rotrsi3 (dst, dst, GEN_INT (shift)));
return 1;
}
}
}
}
return 0;

11
gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c
View file

@ -21,4 +21,15 @@ void test_3(int *p)
*p = 192437;
}
struct foo
{
unsigned int b : 10;
unsigned int g : 11;
unsigned int r : 11;
};
void test_4(struct foo *p, unsigned int v)
{
p->g = v;
}
/* { dg-final { scan-assembler-not "l32r" } } */