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[AArch64] Add combiner patterns for FAC instructions

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gcc/
	* config/aarch64/aarch64-simd.md (*aarch64_fac<optab><mode>): New.
	* config/aarch64/iterators.md (FAC_COMPARISONS): New.

From-SVN: r198494
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James Greenhalgh 2013-05-01 10:46:00 +00:00 • committed by James Greenhalgh
parent ad755ff16d
commit 75dd5aceb2
3 changed files with 25 additions and 0 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_fac<optab><mode>): New.
* config/aarch64/iterators.md (FAC_COMPARISONS): New.
2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-simd.md

17
gcc/config/aarch64/aarch64-simd.md
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@ -3400,6 +3400,23 @@
(set_attr "simd_mode" "<MODE>")]
)
;; fac(ge|gt)
;; Note we can also handle what would be fac(le|lt) by
;; generating fac(ge|gt).
(define_insn "*aarch64_fac<optab><mode>"
[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
(neg:<V_cmp_result>
(FAC_COMPARISONS:<V_cmp_result>
(abs:VALLF (match_operand:VALLF 1 "register_operand" "w"))
(abs:VALLF (match_operand:VALLF 2 "register_operand" "w"))
)))]
"TARGET_SIMD"
"fac<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
[(set_attr "simd_type" "simd_fcmp")
(set_attr "simd_mode" "<MODE>")]
)
;; addp
(define_insn "aarch64_addp<mode>"

3
gcc/config/aarch64/iterators.md
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@ -553,6 +553,9 @@
;; Unsigned comparison operators.
(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
;; Unsigned comparison operators.
(define_code_iterator FAC_COMPARISONS [lt le ge gt])
;; -------------------------------------------------------------------
;; Code Attributes
;; -------------------------------------------------------------------