amdgcn: fix vcc clobber in vector load/store
This switches the code that expands scalar addresses to vectors of addresses from using VCC to using CC_SAVE_REG, for the lo-part to hi-part carry values. These were fine in code expanded in earlier passes, but addresses expanded late, such as for stack spills or reloads, could clobber live VCC values, causing execution failures. This is the first target-specific testcase for GCN, so the new .exp file is included. 2020-05-14 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (add<mode>3_zext_dup): Change to a define_expand, and rename the original to ... (add<mode>3_vcc_zext_dup): ... this, and add a custom VCC operand. (add<mode>3_zext_dup_exec): Likewise, with ... (add<mode>3_vcc_zext_dup_exec): ... this. (add<mode>3_zext_dup2): Likewise, with ... (add<mode>3_zext_dup_exec): ... this. (add<mode>3_zext_dup2_exec): Likewise, with ... (add<mode>3_zext_dup2): ... this. * config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch addv64di3_zext* calls to use addv64di3_vcc_zext*. gcc/testsuite/ * testsuite/gcc.target/gcn/gcn.exp: New file. * testsuite/gcc.target/gcn/vcc-clobber.c: New file.
This commit is contained in:
Andrew Stubbs
parent
9056cd8035
commit
75d0b3d728
6 changed files with 217 additions and 51 deletions
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@ -1,3 +1,17 @@
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2020-05-14 Andrew Stubbs <ams@codesourcery.com>
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* config/gcn/gcn-valu.md (add<mode>3_zext_dup): Change to a
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define_expand, and rename the original to ...
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(add<mode>3_vcc_zext_dup): ... this, and add a custom VCC operand.
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(add<mode>3_zext_dup_exec): Likewise, with ...
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(add<mode>3_vcc_zext_dup_exec): ... this.
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(add<mode>3_zext_dup2): Likewise, with ...
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(add<mode>3_zext_dup_exec): ... this.
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(add<mode>3_zext_dup2_exec): Likewise, with ...
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(add<mode>3_zext_dup2): ... this.
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* config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch
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addv64di3_zext* calls to use addv64di3_vcc_zext*.
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2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
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PR target/95046
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@ -1379,135 +1379,206 @@
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[(set_attr "type" "vmult")
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(set_attr "length" "8")])
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(define_insn_and_split "add<mode>3_zext_dup"
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[(set (match_operand:V_DI 0 "register_operand" "= v, v")
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(define_insn_and_split "add<mode>3_vcc_zext_dup"
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[(set (match_operand:V_DI 0 "register_operand" "= v, v")
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(plus:V_DI
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(zero_extend:V_DI
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(vec_duplicate:<VnSI>
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(match_operand:SI 1 "gcn_alu_operand" "BSv,ASv")))
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(match_operand:V_DI 2 "gcn_alu_operand" "vDA,vDb")))
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(clobber (reg:DI VCC_REG))]
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(match_operand:SI 1 "gcn_alu_operand" " BSv, ASv")))
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(match_operand:V_DI 2 "gcn_alu_operand" " vDA, vDb")))
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(set (match_operand:DI 3 "register_operand" "=SgcV,SgcV")
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(ltu:DI (plus:V_DI
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(zero_extend:V_DI (vec_duplicate:<VnSI> (match_dup 1)))
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(match_dup 2))
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(match_dup 1)))]
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""
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"#"
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"gcn_can_split_p (<MODE>mode, operands[0])
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&& gcn_can_split_p (<MODE>mode, operands[2])"
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[(const_int 0)]
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{
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rtx vcc = gen_rtx_REG (DImode, VCC_REG);
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emit_insn (gen_add<vnsi>3_vcc_dup
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(gcn_operand_part (<MODE>mode, operands[0], 0),
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gcn_operand_part (DImode, operands[1], 0),
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gcn_operand_part (<MODE>mode, operands[2], 0),
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vcc));
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operands[3]));
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emit_insn (gen_addc<vnsi>3
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(gcn_operand_part (<MODE>mode, operands[0], 1),
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gcn_operand_part (<MODE>mode, operands[2], 1),
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const0_rtx, vcc, vcc));
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const0_rtx, operands[3], operands[3]));
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DONE;
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}
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[(set_attr "type" "vmult")
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(set_attr "length" "8")])
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(define_insn_and_split "add<mode>3_zext_dup_exec"
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[(set (match_operand:V_DI 0 "register_operand" "= v, v")
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(define_expand "add<mode>3_zext_dup"
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[(match_operand:V_DI 0 "register_operand")
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(match_operand:SI 1 "gcn_alu_operand")
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(match_operand:V_DI 2 "gcn_alu_operand")]
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""
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{
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rtx vcc = gen_rtx_REG (DImode, VCC_REG);
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emit_insn (gen_add<mode>3_vcc_zext_dup (operands[0], operands[1],
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operands[2], vcc));
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DONE;
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})
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(define_insn_and_split "add<mode>3_vcc_zext_dup_exec"
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[(set (match_operand:V_DI 0 "register_operand" "= v, v")
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(vec_merge:V_DI
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(plus:V_DI
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(zero_extend:V_DI
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(vec_duplicate:<VnSI>
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(match_operand:SI 1 "gcn_alu_operand" "ASv,BSv")))
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(match_operand:V_DI 2 "gcn_alu_operand" "vDb,vDA"))
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(match_operand:V_DI 3 "gcn_register_or_unspec_operand" " U0, U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e, e")))
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(clobber (reg:DI VCC_REG))]
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(match_operand:SI 1 "gcn_alu_operand" " ASv, BSv")))
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(match_operand:V_DI 2 "gcn_alu_operand" " vDb, vDA"))
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(match_operand:V_DI 4 "gcn_register_or_unspec_operand" " U0, U0")
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(match_operand:DI 5 "gcn_exec_reg_operand" " e, e")))
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(set (match_operand:DI 3 "register_operand" "=SgcV,SgcV")
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(and:DI
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(ltu:DI (plus:V_DI
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(zero_extend:V_DI (vec_duplicate:<VnSI> (match_dup 1)))
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(match_dup 2))
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(match_dup 1))
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(match_dup 5)))]
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""
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"#"
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"gcn_can_split_p (<MODE>mode, operands[0])
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&& gcn_can_split_p (<MODE>mode, operands[2])
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&& gcn_can_split_p (<MODE>mode, operands[3])"
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&& gcn_can_split_p (<MODE>mode, operands[4])"
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[(const_int 0)]
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{
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rtx vcc = gen_rtx_REG (DImode, VCC_REG);
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emit_insn (gen_add<vnsi>3_vcc_dup_exec
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(gcn_operand_part (<MODE>mode, operands[0], 0),
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gcn_operand_part (DImode, operands[1], 0),
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gcn_operand_part (<MODE>mode, operands[2], 0),
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vcc,
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gcn_operand_part (<MODE>mode, operands[3], 0),
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operands[4]));
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operands[3],
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gcn_operand_part (<MODE>mode, operands[4], 0),
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operands[5]));
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emit_insn (gen_addc<vnsi>3_exec
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(gcn_operand_part (<MODE>mode, operands[0], 1),
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gcn_operand_part (<MODE>mode, operands[2], 1),
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const0_rtx, vcc, vcc,
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gcn_operand_part (<MODE>mode, operands[3], 1),
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operands[4]));
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const0_rtx, operands[3], operands[3],
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gcn_operand_part (<MODE>mode, operands[4], 1),
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operands[5]));
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DONE;
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}
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[(set_attr "type" "vmult")
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(set_attr "length" "8")])
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(define_insn_and_split "add<mode>3_zext_dup2"
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[(set (match_operand:V_DI 0 "register_operand" "= v")
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(define_expand "add<mode>3_zext_dup_exec"
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[(match_operand:V_DI 0 "register_operand")
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(match_operand:SI 1 "gcn_alu_operand")
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(match_operand:V_DI 2 "gcn_alu_operand")
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(match_operand:V_DI 3 "gcn_register_or_unspec_operand")
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(match_operand:DI 4 "gcn_exec_reg_operand")]
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""
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{
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rtx vcc = gen_rtx_REG (DImode, VCC_REG);
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emit_insn (gen_add<mode>3_vcc_zext_dup_exec (operands[0], operands[1],
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operands[2], vcc, operands[3],
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operands[4]));
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DONE;
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})
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(define_insn_and_split "add<mode>3_vcc_zext_dup2"
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[(set (match_operand:V_DI 0 "register_operand" "= v")
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(plus:V_DI
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(zero_extend:V_DI (match_operand:<VnSI> 1 "gcn_alu_operand" " vA"))
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(vec_duplicate:V_DI (match_operand:DI 2 "gcn_alu_operand" "DbSv"))))
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(clobber (reg:DI VCC_REG))]
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(vec_duplicate:V_DI (match_operand:DI 2 "gcn_alu_operand" " DbSv"))))
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(set (match_operand:DI 3 "register_operand" "=SgcV")
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(ltu:DI (plus:V_DI
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(zero_extend:V_DI (match_dup 1))
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(vec_duplicate:V_DI (match_dup 2)))
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(match_dup 1)))]
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""
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"#"
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"gcn_can_split_p (<MODE>mode, operands[0])"
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[(const_int 0)]
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{
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rtx vcc = gen_rtx_REG (DImode, VCC_REG);
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emit_insn (gen_add<vnsi>3_vcc_dup
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(gcn_operand_part (<MODE>mode, operands[0], 0),
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gcn_operand_part (DImode, operands[2], 0),
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operands[1],
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vcc));
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operands[3]));
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rtx dsthi = gcn_operand_part (<MODE>mode, operands[0], 1);
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emit_insn (gen_vec_duplicate<vnsi>
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(dsthi, gcn_operand_part (DImode, operands[2], 1)));
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emit_insn (gen_addc<vnsi>3 (dsthi, dsthi, const0_rtx, vcc, vcc));
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emit_insn (gen_addc<vnsi>3 (dsthi, dsthi, const0_rtx, operands[3],
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operands[3]));
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DONE;
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}
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[(set_attr "type" "vmult")
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(set_attr "length" "8")])
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(define_insn_and_split "add<mode>3_zext_dup2_exec"
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[(set (match_operand:V_DI 0 "register_operand" "= v")
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(define_expand "add<mode>3_zext_dup2"
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[(match_operand:V_DI 0 "register_operand")
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(match_operand:<VnSI> 1 "gcn_alu_operand")
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(match_operand:DI 2 "gcn_alu_operand")]
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""
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{
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rtx vcc = gen_rtx_REG (DImode, VCC_REG);
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emit_insn (gen_add<mode>3_vcc_zext_dup2 (operands[0], operands[1],
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operands[2], vcc));
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DONE;
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})
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(define_insn_and_split "add<mode>3_vcc_zext_dup2_exec"
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[(set (match_operand:V_DI 0 "register_operand" "= v")
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(vec_merge:V_DI
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(plus:V_DI
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(zero_extend:V_DI (match_operand:<VnSI> 1 "gcn_alu_operand" "vA"))
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(vec_duplicate:V_DI (match_operand:DI 2 "gcn_alu_operand" "BSv")))
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(match_operand:V_DI 3 "gcn_register_or_unspec_operand" " U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e")))
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(clobber (reg:DI VCC_REG))]
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(match_operand:V_DI 4 "gcn_register_or_unspec_operand" " U0")
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(match_operand:DI 5 "gcn_exec_reg_operand" " e")))
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(set (match_operand:DI 3 "register_operand" "=SgcV")
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(and:DI
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(ltu:DI (plus:V_DI
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(zero_extend:V_DI (match_dup 1))
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(vec_duplicate:V_DI (match_dup 2)))
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(match_dup 1))
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(match_dup 5)))]
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""
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"#"
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"gcn_can_split_p (<MODE>mode, operands[0])
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&& gcn_can_split_p (<MODE>mode, operands[3])"
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&& gcn_can_split_p (<MODE>mode, operands[4])"
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[(const_int 0)]
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{
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rtx vcc = gen_rtx_REG (DImode, VCC_REG);
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emit_insn (gen_add<vnsi>3_vcc_dup_exec
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(gcn_operand_part (<MODE>mode, operands[0], 0),
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gcn_operand_part (DImode, operands[2], 0),
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operands[1],
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vcc,
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gcn_operand_part (<MODE>mode, operands[3], 0),
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operands[4]));
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operands[3],
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gcn_operand_part (<MODE>mode, operands[4], 0),
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operands[5]));
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rtx dsthi = gcn_operand_part (<MODE>mode, operands[0], 1);
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emit_insn (gen_vec_duplicate<vnsi>_exec
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(dsthi, gcn_operand_part (DImode, operands[2], 1),
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gcn_operand_part (<MODE>mode, operands[3], 1),
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operands[4]));
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gcn_operand_part (<MODE>mode, operands[4], 1),
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operands[5]));
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emit_insn (gen_addc<vnsi>3_exec
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(dsthi, dsthi, const0_rtx, vcc, vcc,
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gcn_operand_part (<MODE>mode, operands[3], 1),
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operands[4]));
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(dsthi, dsthi, const0_rtx, operands[3], operands[3],
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gcn_operand_part (<MODE>mode, operands[4], 1),
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operands[5]));
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DONE;
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}
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[(set_attr "type" "vmult")
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(set_attr "length" "8")])
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(define_expand "add<mode>3_zext_dup2_exec"
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[(match_operand:V_DI 0 "register_operand")
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(match_operand:<VnSI> 1 "gcn_alu_operand")
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(match_operand:DI 2 "gcn_alu_operand")
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(match_operand:V_DI 3 "gcn_register_or_unspec_operand")
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(match_operand:DI 4 "gcn_exec_reg_operand")]
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""
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{
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rtx vcc = gen_rtx_REG (DImode, VCC_REG);
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emit_insn (gen_add<mode>3_vcc_zext_dup2_exec (operands[0], operands[1],
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operands[2], vcc,
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operands[3], operands[4]));
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DONE;
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})
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(define_insn_and_split "add<mode>3_sext_dup2"
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[(set (match_operand:V_DI 0 "register_operand" "= v")
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(plus:V_DI
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@ -1786,9 +1786,10 @@ gcn_expand_scalar_to_vector_address (machine_mode mode, rtx exec, rtx mem,
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if (AS_FLAT_P (as))
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{
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rtx vcc = gen_rtx_REG (DImode, CC_SAVE_REG);
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if (REG_P (tmp))
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{
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rtx vcc = gen_rtx_REG (DImode, CC_SAVE_REG);
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rtx mem_base_lo = gcn_operand_part (DImode, mem_base, 0);
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rtx mem_base_hi = gcn_operand_part (DImode, mem_base, 1);
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rtx tmphi = gcn_operand_part (V64DImode, tmp, 1);
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@ -1809,17 +1810,17 @@ gcn_expand_scalar_to_vector_address (machine_mode mode, rtx exec, rtx mem,
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vcc, vcc, undef_v64si, exec));
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}
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else
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emit_insn (gen_addv64di3_zext_dup (tmp, mem_base_lo, tmp));
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emit_insn (gen_addv64di3_vcc_zext_dup (tmp, mem_base_lo, tmp, vcc));
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}
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else
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{
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tmp = gen_reg_rtx (V64DImode);
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if (exec)
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emit_insn (gen_addv64di3_zext_dup2_exec (tmp, tmplo, mem_base,
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gcn_gen_undef (V64DImode),
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exec));
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emit_insn (gen_addv64di3_vcc_zext_dup2_exec
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(tmp, tmplo, mem_base, vcc, gcn_gen_undef (V64DImode),
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exec));
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else
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emit_insn (gen_addv64di3_zext_dup2 (tmp, tmplo, mem_base));
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emit_insn (gen_addv64di3_vcc_zext_dup2 (tmp, tmplo, mem_base, vcc));
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}
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new_base = tmp;
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@ -1,3 +1,8 @@
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2020-05-14 Andrew Stubbs <ams@codesourcery.com>
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* testsuite/gcc.target/gcn/gcn.exp: New file.
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* testsuite/gcc.target/gcn/vcc-clobber.c: New file.
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2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
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PR target/95046
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42
gcc/testsuite/gcc.target/gcn/gcn.exp
Normal file
42
gcc/testsuite/gcc.target/gcn/gcn.exp
Normal file
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@ -0,0 +1,42 @@
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# Specific regression driver for nvptx.
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# Copyright (C) 2020 Free Software Foundation, Inc.
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
|
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# along with GCC; see the file COPYING3. If not see
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# <http://www.gnu.org/licenses/>.
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# GCC testsuite that uses the `dg.exp' driver.
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# Exit immediately if this isn't a nvptx target.
|
||||
if ![istarget amdgcn*-*-*] then {
|
||||
return
|
||||
}
|
||||
|
||||
# Load support procs.
|
||||
load_lib gcc-dg.exp
|
||||
|
||||
# If a testcase doesn't have special options, use these.
|
||||
global DEFAULT_CFLAGS
|
||||
if ![info exists DEFAULT_CFLAGS] then {
|
||||
set DEFAULT_CFLAGS " -ansi -pedantic-errors"
|
||||
}
|
||||
|
||||
# Initialize `dg'.
|
||||
dg-init
|
||||
|
||||
# Main loop.
|
||||
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
|
||||
"" $DEFAULT_CFLAGS
|
||||
|
||||
# All done.
|
||||
dg-finish
|
||||
33
gcc/testsuite/gcc.target/gcn/vcc-clobber.c
Normal file
33
gcc/testsuite/gcc.target/gcn/vcc-clobber.c
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-options "-O2" } */
|
||||
|
||||
/* Test that gcn_expand_scalar_to_vector_address does not clobber VCC.
|
||||
If it does then spills and reloads will be unsafe, leading to unexpected
|
||||
conditional branch behaviour. */
|
||||
|
||||
extern void abort ();
|
||||
|
||||
__attribute__((vector_size(256))) int vec[2] = {{0}, {0}};
|
||||
|
||||
int
|
||||
main()
|
||||
{
|
||||
long vcc = 0;
|
||||
|
||||
/* Load a known value into VCC. The memory barrier ensures that the vector
|
||||
load must happen after this point. */
|
||||
asm volatile ("s_mov_b32 vcc_lo, 0x12345689\n\t"
|
||||
"s_mov_b32 vcc_hi, 0xabcdef0"
|
||||
::: "memory");
|
||||
|
||||
/* Compiler inserts vector load here. */
|
||||
|
||||
/* Consume the abitrary vector, and return the current value of VCC. */
|
||||
asm volatile ("; no-op" : "=cV"(vcc) : "v"(vec[0]), "v"(vec[1]));
|
||||
|
||||
/* The value should match the initialized value. */
|
||||
if (vcc != 0xabcdef012345689)
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue