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md.texi: Document that the % constraint character must be at the beginning of the string.

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gcc/
	* doc/md.texi: Document that the % constraint character must
	be at the beginning of the string.
	* genoutput.c (validate_insn_alternatives): Check that '=',
	'+' and '%' only appear at the beginning of a constraint.
	* ira.c (commutative_constraint_p): Delete.
	(ira_get_dup_out_num): Expect the '%' commutativity marker to be
	at the start of the string.
	* config/alpha/alpha.md (*movmemdi_1, *clrmemdi_1): Remove
	duplicate '='s.
	* config/arm/neon.md (bicdi3_neon): Likewise.
	* config/iq2000/iq2000.md (addsi3_internal, subsi3_internal, sgt_si)
	(slt_si, sltu_si): Likewise.
	* config/vax/vax.md (sbcdi3): Likewise.
	* config/h8300/h8300.md (*cmpstz): Remove duplicate '+'.
	* config/arc/arc.md (mulsi_600, mulsidi_600, umulsidi_600)
	(mul64): Move '%' to beginning of constraint.
	* config/arm/arm.md (*xordi3_insn): Likewise.
	* config/nds32/nds32.md (add<mode>3, mulsi3, andsi3, iorsi3)
	(xorsi3): Likewise.

From-SVN: r211031
This commit is contained in:
Richard Sandiford 2014-05-28 19:49:18 +00:00 • committed by Richard Sandiford
parent 5a7555ab10
commit 73f793e3bb
12 changed files with 61 additions and 60 deletions
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22
gcc/ChangeLog
View file

@ -1,3 +1,25 @@
2014-05-28 Richard Sandiford <rdsandiford@googlemail.com>
* doc/md.texi: Document that the % constraint character must
be at the beginning of the string.
* genoutput.c (validate_insn_alternatives): Check that '=',
'+' and '%' only appear at the beginning of a constraint.
* ira.c (commutative_constraint_p): Delete.
(ira_get_dup_out_num): Expect the '%' commutativity marker to be
at the start of the string.
* config/alpha/alpha.md (*movmemdi_1, *clrmemdi_1): Remove
duplicate '='s.
* config/arm/neon.md (bicdi3_neon): Likewise.
* config/iq2000/iq2000.md (addsi3_internal, subsi3_internal, sgt_si)
(slt_si, sltu_si): Likewise.
* config/vax/vax.md (sbcdi3): Likewise.
* config/h8300/h8300.md (*cmpstz): Remove duplicate '+'.
* config/arc/arc.md (mulsi_600, mulsidi_600, umulsidi_600)
(mul64): Move '%' to beginning of constraint.
* config/arm/arm.md (*xordi3_insn): Likewise.
* config/nds32/nds32.md (add<mode>3, mulsi3, andsi3, iorsi3)
(xorsi3): Likewise.
2014-05-28 Richard Sandiford <rdsandiford@googlemail.com>
* doc/md.texi: Document the restrictions on the "enabled" attribute.

4
gcc/config/alpha/alpha.md
View file

@ -4764,7 +4764,7 @@
"operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");")
(define_insn "*movmemdi_1"
[(set (match_operand:BLK 0 "memory_operand" "=m,=m")
[(set (match_operand:BLK 0 "memory_operand" "=m,m")
(match_operand:BLK 1 "memory_operand" "m,m"))
(use (match_operand:DI 2 "nonmemory_operand" "r,i"))
(use (match_operand:DI 3 "immediate_operand"))
@ -4831,7 +4831,7 @@
})
(define_insn "*clrmemdi_1"
[(set (match_operand:BLK 0 "memory_operand" "=m,=m")
[(set (match_operand:BLK 0 "memory_operand" "=m,m")
(const_int 0))
(use (match_operand:DI 1 "nonmemory_operand" "r,i"))
(use (match_operand:DI 2 "immediate_operand"))

8
gcc/config/arc/arc.md
View file

@ -1698,7 +1698,7 @@
(define_insn "mulsi_600"
[(set (match_operand:SI 2 "mlo_operand" "")
(mult:SI (match_operand:SI 0 "register_operand" "Rcq#q,c,c,%c")
(mult:SI (match_operand:SI 0 "register_operand" "%Rcq#q,c,c,c")
(match_operand:SI 1 "nonmemory_operand" "Rcq#q,cL,I,Cal")))
(clobber (match_operand:SI 3 "mhi_operand" ""))]
"TARGET_MUL64_SET"
@ -1750,7 +1750,7 @@
(define_insn "mulsidi_600"
[(set (reg:DI MUL64_OUT_REG)
(mult:DI (sign_extend:DI
(match_operand:SI 0 "register_operand" "Rcq#q,c,c,%c"))
(match_operand:SI 0 "register_operand" "%Rcq#q,c,c,c"))
(sign_extend:DI
; assembler issue for "I", see mulsi_600
; (match_operand:SI 1 "register_operand" "Rcq#q,cL,I,Cal"))))]
@ -1766,7 +1766,7 @@
(define_insn "umulsidi_600"
[(set (reg:DI MUL64_OUT_REG)
(mult:DI (zero_extend:DI
(match_operand:SI 0 "register_operand" "c,c,%c"))
(match_operand:SI 0 "register_operand" "%c,c,c"))
(sign_extend:DI
; assembler issue for "I", see mulsi_600
; (match_operand:SI 1 "register_operand" "cL,I,Cal"))))]
@ -4134,7 +4134,7 @@
;; FIXME: an intrinsic for multiply is daft. Can we remove this?
(define_insn "mul64"
[(unspec [(match_operand:SI 0 "general_operand" "q,r,r,%r")
[(unspec [(match_operand:SI 0 "general_operand" "%q,r,r,r")
(match_operand:SI 1 "general_operand" "q,rL,I,Cal")]
UNSPEC_MUL64)]
"TARGET_MUL64_SET"

2
gcc/config/arm/arm.md
View file

@ -3169,7 +3169,7 @@
(define_insn_and_split "*xordi3_insn"
[(set (match_operand:DI 0 "s_register_operand" "=w,&r,&r,&r,&r,?w")
(xor:DI (match_operand:DI 1 "s_register_operand" "w ,%0,r ,0 ,r ,w")
(xor:DI (match_operand:DI 1 "s_register_operand" "%w ,0,r ,0 ,r ,w")
(match_operand:DI 2 "arm_xordi_operand" "w ,r ,r ,Dg,Dg,w")))]
"TARGET_32BIT && !TARGET_IWMMXT"
{

2
gcc/config/arm/neon.md
View file

@ -728,7 +728,7 @@
;; Compare to *anddi_notdi_di.
(define_insn "bicdi3_neon"
[(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r")
[(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r")
(and:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,r,0"))
(match_operand:DI 1 "s_register_operand" "w,0,r")))]
"TARGET_NEON"

2
gcc/config/h8300/h8300.md
View file

@ -3589,7 +3589,7 @@
[(set_attr "cc" "clobber")])
(define_insn_and_split "*cmpstz"
[(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU,+WU")
[(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU,WU")
(const_int 1)
(match_operand:QI 1 "immediate_operand" "n,n"))
(match_operator:QI 2 "eqne_operator"

10
gcc/config/iq2000/iq2000.md
View file

@ -260,7 +260,7 @@
"")
(define_insn "addsi3_internal"
[(set (match_operand:SI 0 "register_operand" "=d,=d")
[(set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
(match_operand:SI 2 "arith_operand" "d,I")))]
""
@ -286,7 +286,7 @@
"")
(define_insn "subsi3_internal"
[(set (match_operand:SI 0 "register_operand" "=d,=d")
[(set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
(match_operand:SI 2 "arith_operand" "d,I")))]
""
@ -1229,7 +1229,7 @@
(set_attr "mode" "SI")])
(define_insn "sgt_si"
[(set (match_operand:SI 0 "register_operand" "=d,=d")
[(set (match_operand:SI 0 "register_operand" "=d,d")
(gt:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "reg_or_0_operand" "d,J")))]
""
@ -1240,7 +1240,7 @@
(set_attr "mode" "SI,SI")])
(define_insn "slt_si"
[(set (match_operand:SI 0 "register_operand" "=d,=d")
[(set (match_operand:SI 0 "register_operand" "=d,d")
(lt:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "arith_operand" "d,I")))]
""
@ -1273,7 +1273,7 @@
(set_attr "mode" "SI")])
(define_insn "sltu_si"
[(set (match_operand:SI 0 "register_operand" "=d,=d")
[(set (match_operand:SI 0 "register_operand" "=d,d")
(ltu:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "arith_operand" "d,I")))]
""

26
gcc/config/nds32/nds32.md
View file

@ -261,7 +261,7 @@
(define_insn "add<mode>3"
[(set (match_operand:QIHISI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r")
(plus:QIHISI (match_operand:QIHISI 1 "register_operand" " 0, l, 0, l, %0, l, 0, k, r, r")
(plus:QIHISI (match_operand:QIHISI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r")
(match_operand:QIHISI 2 "nds32_rimm15s_operand" " In05, In03, Iu05, Iu03, r, l, Is10, Iu06, Is15, r")))]
""
{
@ -382,9 +382,9 @@
;; Multiplication instructions.
(define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "= w, r")
(mult:SI (match_operand:SI 1 "register_operand" " %0, r")
(match_operand:SI 2 "register_operand" " w, r")))]
[(set (match_operand:SI 0 "register_operand" "=w, r")
(mult:SI (match_operand:SI 1 "register_operand" "%0, r")
(match_operand:SI 2 "register_operand" " w, r")))]
""
"@
mul33\t%0, %2
@ -489,9 +489,9 @@
)
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "= w, r, l, l, l, l, l, l, r, r, r, r, r")
(and:SI (match_operand:SI 1 "register_operand" " %0, r, l, l, l, l, 0, 0, r, r, r, r, r")
(match_operand:SI 2 "general_operand" " w, r, Izeb, Izeh, Ixls, Ix11, Ibms, Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))]
[(set (match_operand:SI 0 "register_operand" "=w, r, l, l, l, l, l, l, r, r, r, r, r")
(and:SI (match_operand:SI 1 "register_operand" "%0, r, l, l, l, l, 0, 0, r, r, r, r, r")
(match_operand:SI 2 "general_operand" " w, r, Izeb, Izeh, Ixls, Ix11, Ibms, Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))]
""
{
HOST_WIDE_INT mask = INTVAL (operands[2]);
@ -585,9 +585,9 @@
;; For V3/V3M ISA, we have 'or33' instruction.
;; So we can identify 'or Rt3,Rt3,Ra3' case and set its length to be 2.
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "= w, r, r, r")
(ior:SI (match_operand:SI 1 "register_operand" " %0, r, r, r")
(match_operand:SI 2 "general_operand" " w, r, Iu15, Ie15")))]
[(set (match_operand:SI 0 "register_operand" "=w, r, r, r")
(ior:SI (match_operand:SI 1 "register_operand" "%0, r, r, r")
(match_operand:SI 2 "general_operand" " w, r, Iu15, Ie15")))]
""
{
int one_position;
@ -645,9 +645,9 @@
;; For V3/V3M ISA, we have 'xor33' instruction.
;; So we can identify 'xor Rt3,Rt3,Ra3' case and set its length to be 2.
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "= w, r, r, r")
(xor:SI (match_operand:SI 1 "register_operand" " %0, r, r, r")
(match_operand:SI 2 "general_operand" " w, r, Iu15, It15")))]
[(set (match_operand:SI 0 "register_operand" "=w, r, r, r")
(xor:SI (match_operand:SI 1 "register_operand" "%0, r, r, r")
(match_operand:SI 2 "general_operand" " w, r, Iu15, It15")))]
""
{
int one_position;

2
gcc/config/vax/vax.md
View file

@ -423,7 +423,7 @@
"vax_expand_addsub_di_operands (operands, MINUS); DONE;")
(define_insn "sbcdi3"
[(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,=Rr")
[(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,Rr")
(minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
(match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))]
"TARGET_QMATH"

5
gcc/doc/md.texi
View file

@ -1589,7 +1589,10 @@ See, for example, the @samp{mulsi3} insn of the ARM@.
Declares the instruction to be commutative for this operand and the
following operand. This means that the compiler may interchange the
two operands if that is the cheapest way to make all operands fit the
constraints.
constraints. @samp{%} applies to all alternatives and must appear as
the first character in the constraint. Only input operands can use
@samp{%}.
@ifset INTERNALS
This is often used in patterns for addition instructions
that really have only two operands: the result must go in one of the

5
gcc/genoutput.c
View file

@ -781,6 +781,11 @@ validate_insn_alternatives (struct data *d)
for (p = d->operand[start].constraint; (c = *p); p += len)
{
if ((c == '%' || c == '=' || c == '+')
&& p != d->operand[start].constraint)
error_with_line (d->lineno,
"character '%c' can only be used at the"
" beginning of a constraint string", c);
#ifdef USE_MD_CONSTRAINTS
if (ISSPACE (c) || strchr (indep_constraints, c))
len = 1;

33
gcc/ira.c
View file

@ -1770,34 +1770,6 @@ setup_prohibited_mode_move_regs (void)
/* Return TRUE if the operand constraint STR is commutative. */
static bool
commutative_constraint_p (const char *str)
{
int c;
alternative_mask enabled = recog_data.enabled_alternatives;
for (;;)
{
c = *str;
if (c == '\0')
break;
str += CONSTRAINT_LEN (c, str);
if (c == '#')
enabled &= ~ALTERNATIVE_BIT (0);
else if (c == ',')
enabled >>= 1;
else if (enabled & 1)
{
/* Usually `%' is the first constraint character but the
documentation does not require this. */
if (c == '%')
return true;
}
}
return false;
}
/* Setup possible alternatives in ALTS for INSN. */
void
ira_setup_alts (rtx insn, HARD_REG_SET &alts)
@ -2099,10 +2071,9 @@ ira_get_dup_out_num (int op_num, HARD_REG_SET &alts)
if (use_commut_op_p)
break;
use_commut_op_p = true;
if (commutative_constraint_p (recog_data.constraints[op_num]))
if (recog_data.constraints[op_num][0] == '%')
str = recog_data.constraints[op_num + 1];
else if (op_num > 0 && commutative_constraint_p (recog_data.constraints
[op_num - 1]))
else if (op_num > 0 && recog_data.constraints[op_num - 1][0] == '%')
str = recog_data.constraints[op_num - 1];
else
break;