re PR target/38287 (segfault at -O2 -fPIC -mcpu=v8)
PR target/38287 * config/sparc/sparc.md (divsi3 expander): Remove constraints. (divsi3_sp32): Add new alternative with 'K' for operand #2. (cmp_sdiv_cc_set): Factor common string. (udivsi3_sp32): Add new alternative with 'K' for operand #2. Add TARGET_V9 case. (cmp_udiv_cc_set): Factor common string. From-SVN: r142295
This commit is contained in:
Eric Botcazou
Eric Botcazou
parent
07c9463afe
commit
72b415c586
4 changed files with 131 additions and 42 deletions
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@ -1,3 +1,13 @@
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2008-11-30 Eric Botcazou <ebotcazou@adacore.com>
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PR target/38287
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* config/sparc/sparc.md (divsi3 expander): Remove constraints.
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(divsi3_sp32): Add new alternative with 'K' for operand #2.
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(cmp_sdiv_cc_set): Factor common string.
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(udivsi3_sp32): Add new alternative with 'K' for operand #2.
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Add TARGET_V9 case.
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(cmp_udiv_cc_set): Factor common string.
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2008-11-30 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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PR middle-end/38283
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@ -4895,14 +4895,11 @@
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[(set_attr "type" "multi")
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(set_attr "length" "2")])
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;; The V8 architecture specifies that there must be 3 instructions between
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;; a Y register write and a use of it for correct results.
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(define_expand "divsi3"
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[(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
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(div:SI (match_operand:SI 1 "register_operand" "r,r")
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(match_operand:SI 2 "input_operand" "rI,m")))
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(clobber (match_scratch:SI 3 "=&r,&r"))])]
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(div:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "input_operand" "")))
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(clobber (match_scratch:SI 3 ""))])]
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"TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
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{
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if (TARGET_ARCH64)
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@ -4915,24 +4912,40 @@
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}
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})
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;; The V8 architecture specifies that there must be at least 3 instructions
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;; between a write to the Y register and a use of it for correct results.
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;; We try to fill one of them with a simple constant or a memory load.
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(define_insn "divsi3_sp32"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(div:SI (match_operand:SI 1 "register_operand" "r,r")
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(match_operand:SI 2 "input_operand" "rI,m")))
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(clobber (match_scratch:SI 3 "=&r,&r"))]
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"(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS)
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&& TARGET_ARCH32"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(div:SI (match_operand:SI 1 "register_operand" "r,r,r")
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(match_operand:SI 2 "input_operand" "rI,K,m")))
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(clobber (match_scratch:SI 3 "=&r,&r,&r"))]
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"(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32"
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{
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if (which_alternative == 0)
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if (TARGET_V9)
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return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdiv\t%1, %2, %0";
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else
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return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdiv\t%1, %2, %0";
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else
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if (TARGET_V9)
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return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tsdiv\t%1, %3, %0";
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else
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return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0";
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output_asm_insn ("sra\t%1, 31, %3", operands);
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output_asm_insn ("wr\t%3, 0, %%y", operands);
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switch (which_alternative)
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{
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case 0:
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if (TARGET_V9)
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return "sdiv\t%1, %2, %0";
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else
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return "nop\n\tnop\n\tnop\n\tsdiv\t%1, %2, %0";
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case 1:
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if (TARGET_V9)
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return "sethi\t%%hi(%a2), %3\n\tsdiv\t%1, %3, %0";
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else
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return "sethi\t%%hi(%a2), %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0";
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case 2:
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if (TARGET_V9)
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return "ld\t%2, %3\n\tsdiv\t%1, %3, %0";
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else
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return "ld\t%2, %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "multi")
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(set (attr "length")
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@ -4967,10 +4980,13 @@
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(clobber (match_scratch:SI 3 "=&r"))]
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"TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
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{
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output_asm_insn ("sra\t%1, 31, %3", operands);
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output_asm_insn ("wr\t%3, 0, %%y", operands);
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if (TARGET_V9)
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return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdivcc\t%1, %2, %0";
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return "sdivcc\t%1, %2, %0";
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else
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return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdivcc\t%1, %2, %0";
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return "nop\n\tnop\n\tnop\n\tsdivcc\t%1, %2, %0";
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}
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[(set_attr "type" "multi")
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(set (attr "length")
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@ -4985,29 +5001,48 @@
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"TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
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"")
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;; The V8 architecture specifies that there must be 3 instructions between
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;; a Y register write and a use of it for correct results.
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;; The V8 architecture specifies that there must be at least 3 instructions
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;; between a write to the Y register and a use of it for correct results.
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;; We try to fill one of them with a simple constant or a memory load.
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(define_insn "udivsi3_sp32"
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[(set (match_operand:SI 0 "register_operand" "=r,&r,&r")
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(udiv:SI (match_operand:SI 1 "nonimmediate_operand" "r,r,m")
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(match_operand:SI 2 "input_operand" "rI,m,r")))]
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"(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS)
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&& TARGET_ARCH32"
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[(set (match_operand:SI 0 "register_operand" "=r,&r,&r,&r")
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(udiv:SI (match_operand:SI 1 "nonimmediate_operand" "r,r,r,m")
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(match_operand:SI 2 "input_operand" "rI,K,m,r")))]
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"(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32"
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{
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output_asm_insn ("wr\t%%g0, %%g0, %%y", operands);
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output_asm_insn ("wr\t%%g0, 0, %%y", operands);
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switch (which_alternative)
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{
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default:
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return "nop\n\tnop\n\tnop\n\tudiv\t%1, %2, %0";
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case 0:
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if (TARGET_V9)
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return "udiv\t%1, %2, %0";
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else
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return "nop\n\tnop\n\tnop\n\tudiv\t%1, %2, %0";
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case 1:
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return "ld\t%2, %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0";
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if (TARGET_V9)
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return "sethi\t%%hi(%a2), %0\n\tudiv\t%1, %0, %0";
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else
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return "sethi\t%%hi(%a2), %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0";
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case 2:
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return "ld\t%1, %0\n\tnop\n\tnop\n\tudiv\t%0, %2, %0";
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if (TARGET_V9)
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return "ld\t%2, %0\n\tudiv\t%1, %0, %0";
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else
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return "ld\t%2, %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0";
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case 3:
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if (TARGET_V9)
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return "ld\t%1, %0\n\tudiv\t%0, %2, %0";
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else
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return "ld\t%1, %0\n\tnop\n\tnop\n\tudiv\t%0, %2, %0";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "multi")
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(set_attr "length" "5")])
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(set (attr "length")
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(if_then_else (eq_attr "isa" "v9")
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(const_int 3) (const_int 5)))])
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(define_insn "udivsi3_sp64"
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[(set (match_operand:SI 0 "register_operand" "=r")
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@ -5033,13 +5068,14 @@
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(udiv:SI (match_dup 1) (match_dup 2)))]
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"TARGET_V8
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|| TARGET_DEPRECATED_V8_INSNS"
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"TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
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{
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output_asm_insn ("wr\t%%g0, 0, %%y", operands);
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if (TARGET_V9)
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return "wr\t%%g0, %%g0, %%y\n\tudivcc\t%1, %2, %0";
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return "udivcc\t%1, %2, %0";
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else
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return "wr\t%%g0, %%g0, %%y\n\tnop\n\tnop\n\tnop\n\tudivcc\t%1, %2, %0";
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return "nop\n\tnop\n\tnop\n\tudivcc\t%1, %2, %0";
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}
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[(set_attr "type" "multi")
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(set (attr "length")
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@ -1,3 +1,7 @@
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2008-11-30 Eric Botcazou <ebotcazou@adacore.com>
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* g++.dg/opt/reload3.C: New test.
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2008-11-30 Paul Thomas <pault@gcc.gnu.org>
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PR fortran/35824
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39
gcc/testsuite/g++.dg/opt/reload3.C
Normal file
39
gcc/testsuite/g++.dg/opt/reload3.C
Normal file
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@ -0,0 +1,39 @@
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// PR target/38287
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// { dg-do run }
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// { dg-options "-O2 -mcpu=v8 -fPIC" { target { { sparc*-*-* } && { ilp32 && fpic } } } }
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#include <cstdlib>
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class QTime
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{
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public:
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explicit QTime(int ms = 0) : ds(ms) {}
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static QTime currentTime() { return QTime(); }
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QTime addMSecs(int ms) const;
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int msecs() const { return ds; }
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private:
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unsigned ds;
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};
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static const unsigned MSECS_PER_DAY = 86400000;
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QTime QTime::addMSecs(int ms) const
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{
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QTime t;
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if ( ms < 0 ) {
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// % not well-defined for -ve, but / is.
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int negdays = (MSECS_PER_DAY-ms) / MSECS_PER_DAY;
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t.ds = ((int)ds + ms + negdays*MSECS_PER_DAY)
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% MSECS_PER_DAY;
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} else {
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t.ds = ((int)ds + ms) % MSECS_PER_DAY;
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}
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return t;
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}
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int main()
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{
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if (QTime(1).addMSecs(1).msecs() != 2)
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abort ();
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return 0;
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}
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