i386: Zhaoxin shijidadao enablement
This patch enables -march/-mtune=shijidadao, costs and tunings are set according to the characteristics of the processor. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Recognize shijidadao. * common/config/i386/i386-common.cc: Add shijidadao. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add ZHAOXIN_FAM7H_SHIJIDADAO. * config.gcc: Add shijidadao. * config/i386/driver-i386.cc (host_detect_local_cpu): Let -march=native recognize shijidadao processors. * config/i386/i386-c.cc (ix86_target_macros_internal): Add shijidadao. * config/i386/i386-options.cc (m_ZHAOXIN): Add m_SHIJIDADAO. (m_SHIJIDADAO): New definition. * config/i386/i386.h (enum processor_type): Add PROCESSOR_SHIJIDADAO. * config/i386/x86-tune-costs.h (struct processor_costs): Add shijidadao_cost. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add shijidadao. (ix86_adjust_cost): Ditto. * config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Add m_SHIJIDADAO. (X86_TUNE_USE_GATHER_4PARTS): Ditto. (X86_TUNE_USE_GATHER_8PARTS): Ditto. (X86_TUNE_AVOID_128FMA_CHAINS): Ditto. * doc/extend.texi: Add details about shijidadao. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv32.C: Handle new -march * gcc.target/i386/funcspec-56.inc: Ditto.
This commit is contained in:
mayshao
Uros Bizjak
parent
0982552bc4
commit
6f6ea27d17
15 changed files with 183 additions and 14 deletions
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@ -667,12 +667,18 @@ get_zhaoxin_cpu (struct __processor_model *cpu_model,
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reset_cpu_feature (cpu_model, cpu_features2, FEATURE_F16C);
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cpu_model->__cpu_subtype = ZHAOXIN_FAM7H_LUJIAZUI;
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}
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else if (model >= 0x5b)
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else if (model == 0x5b)
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{
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cpu = "yongfeng";
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CHECK___builtin_cpu_is ("yongfeng");
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cpu_model->__cpu_subtype = ZHAOXIN_FAM7H_YONGFENG;
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}
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else if (model >= 0x6b)
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{
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cpu = "shijidadao";
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CHECK___builtin_cpu_is ("shijidadao");
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cpu_model->__cpu_subtype = ZHAOXIN_FAM7H_SHIJIDADAO;
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}
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break;
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default:
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break;
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@ -2066,6 +2066,7 @@ const char *const processor_names[] =
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"intel",
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"lujiazui",
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"yongfeng",
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"shijidadao",
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"geode",
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"k6",
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"athlon",
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@ -2271,10 +2272,13 @@ const pta processor_alias_table[] =
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| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
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{"lujiazui", PROCESSOR_LUJIAZUI, CPU_LUJIAZUI,
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PTA_LUJIAZUI,
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M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_NONE},
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M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_PROC_BMI},
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{"yongfeng", PROCESSOR_YONGFENG, CPU_YONGFENG,
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PTA_YONGFENG,
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M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG), P_NONE},
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M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG), P_PROC_AVX2},
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{"shijidadao", PROCESSOR_SHIJIDADAO, CPU_YONGFENG,
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PTA_YONGFENG,
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M_CPU_SUBTYPE (ZHAOXIN_FAM7H_SHIJIDADAO), P_PROC_AVX2},
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{"k8", PROCESSOR_K8, CPU_K8,
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PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
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| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
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@ -104,6 +104,7 @@ enum processor_subtypes
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INTEL_COREI7_PANTHERLAKE,
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ZHAOXIN_FAM7H_YONGFENG,
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AMDFAM1AH_ZNVER5,
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ZHAOXIN_FAM7H_SHIJIDADAO,
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CPU_SUBTYPE_MAX
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};
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@ -711,9 +711,9 @@ atom slm nehalem westmere sandybridge ivybridge haswell broadwell bonnell \
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silvermont skylake-avx512 cannonlake icelake-client icelake-server \
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skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \
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sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \
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nano-x2 eden-x4 nano-x4 lujiazui yongfeng x86-64 x86-64-v2 x86-64-v3 x86-64-v4 \
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sierraforest graniterapids graniterapids-d grandridge arrowlake arrowlake-s \
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clearwaterforest pantherlake native"
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nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \
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x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \
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arrowlake arrowlake-s clearwaterforest pantherlake native"
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# Additional x86 processors supported by --with-cpu=. Each processor
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# MUST be separated by exactly one space.
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@ -3855,6 +3855,10 @@ case ${target} in
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arch=yongfeng
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cpu=yongfeng
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;;
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shijidadao-*)
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arch=shijidadao
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cpu=shijidadao
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;;
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pentium2-*)
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arch=pentium2
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cpu=pentium2
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@ -3980,6 +3984,10 @@ case ${target} in
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arch=yongfeng
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cpu=yongfeng
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;;
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shijidadao-*)
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arch=shijidadao
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cpu=shijidadao
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;;
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nocona-*)
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arch=nocona
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cpu=nocona
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@ -558,10 +558,12 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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switch (family)
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{
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case 7:
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if (model == 0x3b)
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processor = PROCESSOR_LUJIAZUI;
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else if (model >= 0x5b)
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if (model >= 0x6b)
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processor = PROCESSOR_SHIJIDADAO;
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else if (model == 0x5b)
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processor = PROCESSOR_YONGFENG;
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else if (model == 0x3b)
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processor = PROCESSOR_LUJIAZUI;
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break;
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default:
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break;
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@ -853,6 +855,9 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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case PROCESSOR_YONGFENG:
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cpu = "yongfeng";
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break;
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case PROCESSOR_SHIJIDADAO:
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cpu = "shijidadao";
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break;
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default:
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/* Use something reasonable. */
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@ -156,6 +156,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__yongfeng");
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def_or_undef (parse_in, "__yongfeng__");
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break;
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case PROCESSOR_SHIJIDADAO:
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def_or_undef (parse_in, "__shijidadao");
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def_or_undef (parse_in, "__shijidadao__");
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break;
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case PROCESSOR_PENTIUM4:
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def_or_undef (parse_in, "__pentium4");
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def_or_undef (parse_in, "__pentium4__");
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@ -386,6 +390,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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case PROCESSOR_YONGFENG:
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def_or_undef (parse_in, "__tune_yongfeng__");
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break;
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case PROCESSOR_SHIJIDADAO:
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def_or_undef (parse_in, "__tune_shijidadao__");
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break;
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case PROCESSOR_PENTIUM4:
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def_or_undef (parse_in, "__tune_pentium4__");
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break;
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@ -155,7 +155,8 @@ along with GCC; see the file COPYING3. If not see
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#define m_LUJIAZUI (HOST_WIDE_INT_1U<<PROCESSOR_LUJIAZUI)
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#define m_YONGFENG (HOST_WIDE_INT_1U<<PROCESSOR_YONGFENG)
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#define m_ZHAOXIN (m_LUJIAZUI | m_YONGFENG)
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#define m_SHIJIDADAO (HOST_WIDE_INT_1U<<PROCESSOR_SHIJIDADAO)
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#define m_ZHAOXIN (m_LUJIAZUI | m_YONGFENG | m_SHIJIDADAO)
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#define m_GEODE (HOST_WIDE_INT_1U<<PROCESSOR_GEODE)
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#define m_K6 (HOST_WIDE_INT_1U<<PROCESSOR_K6)
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@ -793,6 +794,7 @@ static const struct processor_costs *processor_cost_table[] =
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&intel_cost,
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&lujiazui_cost,
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&yongfeng_cost,
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&shijidadao_cost,
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&geode_cost,
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&k6_cost,
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&athlon_cost,
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@ -2304,6 +2304,7 @@ enum processor_type
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PROCESSOR_INTEL,
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PROCESSOR_LUJIAZUI,
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PROCESSOR_YONGFENG,
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PROCESSOR_SHIJIDADAO,
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PROCESSOR_GEODE,
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PROCESSOR_K6,
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PROCESSOR_ATHLON,
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@ -3644,6 +3644,122 @@ struct processor_costs yongfeng_cost = {
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2, /* Small unroll factor. */
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};
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/* shijidadao_cost should produce code tuned for ZHAOXIN shijidadao CPU. */
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static stringop_algs shijidadao_memcpy[2] = {
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{libcall, {{8, unrolled_loop, true}, {256, unrolled_loop, false},
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{-1, libcall, false}}},
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{libcall, {{10, loop, true}, {256, unrolled_loop, false},
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{-1, libcall, false}}}};
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static stringop_algs shijidadao_memset[2] = {
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{libcall, {{4, loop, true}, {128, unrolled_loop, false},
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{-1, libcall, false}}},
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{libcall, {{1, rep_prefix_4_byte, false}, {14, loop, true},
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{1024, vector_loop, false},
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{-1, libcall, false}}}};
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static const
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struct processor_costs shijidadao_cost = {
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{
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/* Start of register allocator costs. integer->integer move cost is 2. */
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8, /* cost for loading QImode using movzbl. */
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{8, 8, 8}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{8, 8, 8}, /* cost of storing integer registers. */
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2, /* cost of reg,reg fld/fst. */
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{8, 8, 8}, /* cost of loading fp registers
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in SFmode, DFmode and XFmode. */
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{8, 8, 8}, /* cost of storing fp registers
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in SFmode, DFmode and XFmode. */
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2, /* cost of moving MMX register. */
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{8, 8}, /* cost of loading MMX registers
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in SImode and DImode. */
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{8, 8}, /* cost of storing MMX registers
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in SImode and DImode. */
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2, 3, 4, /* cost of moving XMM,YMM,ZMM register. */
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{8, 8, 8, 10, 15}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit. */
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{8, 8, 8, 10, 15}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit. */
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8, 8, /* SSE->integer and integer->SSE moves. */
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8, 8, /* mask->integer and integer->mask moves. */
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{8, 8, 8}, /* cost of loading mask register
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in QImode, HImode, SImode. */
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{8, 8, 8}, /* cost if storing mask register
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in QImode, HImode, SImode. */
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2, /* cost of moving mask register. */
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/* End of register allocator costs. */
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},
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COSTS_N_INSNS (1), /* cost of an add instruction. */
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COSTS_N_INSNS (1), /* cost of a lea instruction. */
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COSTS_N_INSNS (1), /* variable shift costs. */
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COSTS_N_INSNS (1), /* constant shift costs. */
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{COSTS_N_INSNS (2), /* cost of starting multiply for QI. */
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COSTS_N_INSNS (3), /* HI. */
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COSTS_N_INSNS (2), /* SI. */
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COSTS_N_INSNS (2), /* DI. */
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COSTS_N_INSNS (3)}, /* other. */
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0, /* cost of multiply per each bit set. */
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{COSTS_N_INSNS (9), /* cost of a divide/mod for QI. */
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COSTS_N_INSNS (10), /* HI. */
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COSTS_N_INSNS (9), /* SI. */
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COSTS_N_INSNS (50), /* DI. */
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COSTS_N_INSNS (50)}, /* other. */
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COSTS_N_INSNS (1), /* cost of movsx. */
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COSTS_N_INSNS (1), /* cost of movzx. */
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8, /* "large" insn. */
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17, /* MOVE_RATIO. */
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6, /* CLEAR_RATIO. */
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{8, 8, 8}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{8, 8, 8}, /* cost of storing integer registers. */
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{8, 8, 8, 12, 15}, /* cost of loading SSE register
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in 32bit, 64bit, 128bit, 256bit and 512bit. */
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{8, 8, 8, 12, 15}, /* cost of storing SSE register
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in 32bit, 64bit, 128bit, 256bit and 512bit. */
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{8, 8, 8, 12, 15}, /* cost of unaligned loads. */
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{8, 8, 8, 12, 15}, /* cost of unaligned storess. */
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2, 3, 4, /* cost of moving XMM,YMM,ZMM register. */
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8, /* cost of moving SSE register to integer. */
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18, 6, /* Gather load static, per_elt. */
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18, 6, /* Gather store static, per_elt. */
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32, /* size of l1 cache. */
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256, /* size of l2 cache. */
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64, /* size of prefetch block. */
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12, /* number of parallel prefetches. */
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3, /* Branch cost. */
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COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
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COSTS_N_INSNS (3), /* cost of FMUL instruction. */
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COSTS_N_INSNS (13), /* cost of FDIV instruction. */
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COSTS_N_INSNS (2), /* cost of FABS instruction. */
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COSTS_N_INSNS (2), /* cost of FCHS instruction. */
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COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
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COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
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COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */
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COSTS_N_INSNS (3), /* cost of MULSS instruction. */
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COSTS_N_INSNS (3), /* cost of MULSD instruction. */
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COSTS_N_INSNS (5), /* cost of FMA SS instruction. */
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COSTS_N_INSNS (5), /* cost of FMA SD instruction. */
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COSTS_N_INSNS (11), /* cost of DIVSS instruction. */
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COSTS_N_INSNS (14), /* cost of DIVSD instruction. */
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COSTS_N_INSNS (11), /* cost of SQRTSS instruction. */
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COSTS_N_INSNS (18), /* cost of SQRTSD instruction. */
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4, 4, 4, 4, /* reassoc int, fp, vec_int, vec_fp. */
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shijidadao_memcpy,
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shijidadao_memset,
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COSTS_N_INSNS (3), /* cond_taken_branch_cost. */
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COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */
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"16:11:8", /* Loop alignment. */
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"16:11:8", /* Jump alignment. */
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"0:0:8", /* Label alignment. */
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"16", /* Func alignment. */
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4, /* Small unroll limit. */
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2, /* Small unroll factor. */
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};
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/* Generic should produce code tuned for Core-i7 (and newer chips)
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and btver1 (and newer chips). */
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@ -79,6 +79,7 @@ ix86_issue_rate (void)
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case PROCESSOR_CANNONLAKE:
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case PROCESSOR_ALDERLAKE:
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case PROCESSOR_YONGFENG:
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case PROCESSOR_SHIJIDADAO:
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case PROCESSOR_GENERIC:
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return 4;
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@ -446,6 +447,7 @@ ix86_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
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break;
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case PROCESSOR_YONGFENG:
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case PROCESSOR_SHIJIDADAO:
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/* Stack engine allows to execute push&pop instructions in parallel. */
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if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
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&& (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
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@ -477,7 +477,7 @@ DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes",
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elements. */
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DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts",
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~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_CORE_HYBRID
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| m_YONGFENG | m_CORE_ATOM | m_GENERIC | m_GDS))
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| m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))
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/* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2
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elements. */
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@ -488,7 +488,7 @@ DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts",
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elements. */
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DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts",
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~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_CORE_HYBRID
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| m_YONGFENG | m_CORE_ATOM | m_GENERIC | m_GDS))
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| m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))
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/* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4
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elements. */
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@ -499,7 +499,7 @@ DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts",
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elements. */
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DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "use_gather_8parts",
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~(m_ZNVER1 | m_ZNVER2 | m_ZNVER4 | m_CORE_HYBRID | m_CORE_ATOM
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| m_YONGFENG | m_GENERIC | m_GDS))
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| m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_GDS))
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/* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more
|
||||
elements. */
|
||||
|
|
@ -509,7 +509,7 @@ DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, "use_scatter_8parts",
|
|||
/* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
|
||||
smaller FMA chain. */
|
||||
DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4
|
||||
| m_YONGFENG | m_GENERIC)
|
||||
| m_YONGFENG | m_SHIJIDADAO | m_GENERIC)
|
||||
|
||||
/* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or
|
||||
smaller FMA chain. */
|
||||
|
|
|
|||
|
|
@ -26245,6 +26245,9 @@ ZHAOXIN lujiazui CPU.
|
|||
@item yongfeng
|
||||
ZHAOXIN yongfeng CPU.
|
||||
|
||||
@item shijidadao
|
||||
ZHAOXIN shijidadao CPU.
|
||||
|
||||
@item amdfam10h
|
||||
AMD Family 10h CPU.
|
||||
|
||||
|
|
|
|||
|
|
@ -34873,6 +34873,12 @@ SSE4.2, AVX, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16,
|
|||
ABM, BMI, BMI2, F16C, FXSR, RDSEED, AVX2, FMA, SHA, LZCNT
|
||||
instruction set support.
|
||||
|
||||
@item shijidadao
|
||||
ZHAOXIN shijidadao CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
|
||||
SSE4.2, AVX, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16,
|
||||
ABM, BMI, BMI2, F16C, FXSR, RDSEED, AVX2, FMA, SHA, LZCNT
|
||||
instruction set support.
|
||||
|
||||
@item geode
|
||||
AMD Geode embedded processor with MMX and 3DNow!@: instruction set support.
|
||||
@end table
|
||||
|
|
|
|||
|
|
@ -21,6 +21,10 @@ int __attribute__ ((target("arch=yongfeng"))) foo () {
|
|||
return 2;
|
||||
}
|
||||
|
||||
int __attribute__ ((target("arch=shijidadao"))) foo () {
|
||||
return 3;
|
||||
}
|
||||
|
||||
int main ()
|
||||
{
|
||||
int val = foo ();
|
||||
|
|
@ -29,6 +33,8 @@ int main ()
|
|||
assert (val == 1);
|
||||
else if (__builtin_cpu_is ("yongfeng"))
|
||||
assert (val == 2);
|
||||
else if (__builtin_cpu_is ("shijidadao"))
|
||||
assert (val == 3);
|
||||
else
|
||||
assert (val == 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -208,6 +208,7 @@ extern void test_arch_arrowlake_s (void) __attribute__((__target__("arch=arrowla
|
|||
extern void test_arch_pantherlake (void) __attribute__((__target__("arch=pantherlake")));
|
||||
extern void test_arch_lujiazui (void) __attribute__((__target__("arch=lujiazui")));
|
||||
extern void test_arch_yongfeng (void) __attribute__((__target__("arch=yongfeng")));
|
||||
extern void test_arch_shijidadao (void) __attribute__((__target__("arch=shijidadao")));
|
||||
extern void test_arch_k8 (void) __attribute__((__target__("arch=k8")));
|
||||
extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3")));
|
||||
extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron")));
|
||||
|
|
@ -233,6 +234,7 @@ extern void test_tune_corei7_avx (void) __attribute__((__target__("tune=corei7-
|
|||
extern void test_tune_core_avx2 (void) __attribute__((__target__("tune=core-avx2")));
|
||||
extern void test_tune_lujiazui (void) __attribute__((__target__("tune=lujiazui")));
|
||||
extern void test_tune_yongfeng (void) __attribute__((__target__("tune=yongfeng")));
|
||||
extern void test_tune_shijidadao (void) __attribute__((__target__("tune=shijidadao")));
|
||||
extern void test_tune_k8 (void) __attribute__((__target__("tune=k8")));
|
||||
extern void test_tune_k8_sse3 (void) __attribute__((__target__("tune=k8-sse3")));
|
||||
extern void test_tune_opteron (void) __attribute__((__target__("tune=opteron")));
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue