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RISC-V: Add vector related pipelines

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Creates new generic vector pipeline file common to all cpu tunes.
Moves all vector related pipelines from generic-ooo to generic-vector-ooo.
Creates new vector crypto related insn reservations.

gcc/ChangeLog:

	* config/riscv/generic-ooo.md (generic_ooo): Move reservation
	(generic_ooo_vec_load): Ditto
	(generic_ooo_vec_store): Ditto
	(generic_ooo_vec_loadstore_seg): Ditto
	(generic_ooo_vec_alu): Ditto
	(generic_ooo_vec_fcmp): Ditto
	(generic_ooo_vec_imul): Ditto
	(generic_ooo_vec_fadd): Ditto
	(generic_ooo_vec_fmul): Ditto
	(generic_ooo_crypto): Ditto
	(generic_ooo_perm): Ditto
	(generic_ooo_vec_reduction): Ditto
	(generic_ooo_vec_ordered_reduction): Ditto
	(generic_ooo_vec_idiv): Ditto
	(generic_ooo_vec_float_divsqrt): Ditto
	(generic_ooo_vec_mask): Ditto
	(generic_ooo_vec_vesetvl): Ditto
	(generic_ooo_vec_setrm): Ditto
	(generic_ooo_vec_readlen): Ditto
	* config/riscv/riscv.md: Include generic-vector-ooo
	* config/riscv/generic-vector-ooo.md: New file. To here

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Robin Dapp <rdapp.gcc@gmail.com>
This commit is contained in:
Edwin Lu 2024-02-14 12:03:37 -08:00
parent 57b95223cb
commit 6ec84c45a1
3 changed files with 145 additions and 126 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

127
gcc/config/riscv/generic-ooo.md
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@ -1,5 +1,5 @@
;; RISC-V generic out-of-order core scheduling model.
;; Copyright (C) 2017-2024 Free Software Foundation, Inc.
;; Copyright (C) 2023-2024 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
@ -48,9 +48,6 @@
;; Integer/float issue queues.
(define_cpu_unit "issue0,issue1,issue2,issue3,issue4" "generic_ooo")
;; Separate issue queue for vector instructions.
(define_cpu_unit "generic_ooo_vxu_issue" "generic_ooo")
;; Integer/float execution units.
(define_cpu_unit "ixu0,ixu1,ixu2,ixu3" "generic_ooo")
(define_cpu_unit "fxu0,fxu1" "generic_ooo")
@ -58,12 +55,6 @@
;; Integer subunit for division.
(define_cpu_unit "generic_ooo_div" "generic_ooo")
;; Vector execution unit.
(define_cpu_unit "generic_ooo_vxu_alu" "generic_ooo")
;; Vector subunit that does mult/div/sqrt.
(define_cpu_unit "generic_ooo_vxu_multicycle" "generic_ooo")
;; Shortcuts
(define_reservation "generic_ooo_issue" "issue0|issue1|issue2|issue3|issue4")
(define_reservation "generic_ooo_ixu_alu" "ixu0|ixu1|ixu2|ixu3")
@ -92,25 +83,6 @@
(eq_attr "type" "fpstore"))
"generic_ooo_issue,generic_ooo_fxu")
;; Vector load/store
(define_insn_reservation "generic_ooo_vec_load" 6
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
(define_insn_reservation "generic_ooo_vec_store" 6
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector segment loads/stores.
(define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
vssegte,vssegts,vssegtux,vssegtox"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Generic integer instructions.
(define_insn_reservation "generic_ooo_alu" 1
(and (eq_attr "tune" "generic_ooo")
@ -191,103 +163,6 @@
(eq_attr "type" "cpop,clmul"))
"generic_ooo_issue,generic_ooo_ixu_alu")
;; Regular vector operations and integer comparisons.
(define_insn_reservation "generic_ooo_vec_alu" 3
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector float comparison, conversion etc.
(define_insn_reservation "generic_ooo_vec_fcmp" 3
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\
vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
vfncvtftoi,vfncvtftof"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector integer multiplication.
(define_insn_reservation "generic_ooo_vec_imul" 4
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector float addition.
(define_insn_reservation "generic_ooo_vec_fadd" 4
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vfalu,vfwalu"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector float multiplication and FMA.
(define_insn_reservation "generic_ooo_vec_fmul" 6
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector crypto, assumed to be a generic operation for now.
(define_insn_reservation "generic_ooo_crypto" 4
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "crypto"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector permute.
(define_insn_reservation "generic_ooo_perm" 3
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\
vislide1down,vfslide1up,vfslide1down,vgather,vcompress"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector reduction.
(define_insn_reservation "generic_ooo_vec_reduction" 8
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vired,viwred,vfredu,vfwredu"))
"generic_ooo_vxu_issue,generic_ooo_vxu_multicycle")
;; Vector ordered reduction, assume the latency number is for
;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost
;; for larger vectors.
(define_insn_reservation "generic_ooo_vec_ordered_reduction" 10
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vfredo,vfwredo"))
"generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3")
;; Vector integer division, assume not pipelined.
(define_insn_reservation "generic_ooo_vec_idiv" 16
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vidiv"))
"generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3")
;; Vector float divisions and sqrt, assume not pipelined.
(define_insn_reservation "generic_ooo_vec_float_divsqrt" 16
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vfdiv,vfsqrt"))
"generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3")
;; Vector mask operations.
(define_insn_reservation "generic_ooo_vec_mask" 2
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\
vfmovvf,vfmovfv"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector vsetvl.
(define_insn_reservation "generic_ooo_vec_vesetvl" 1
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vsetvl,vsetvl_pre"))
"generic_ooo_vxu_issue")
;; Vector rounding mode setters, assume pipeline barrier.
(define_insn_reservation "generic_ooo_vec_setrm" 20
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "wrvxrm,wrfrm"))
"generic_ooo_vxu_issue,generic_ooo_vxu_issue*3")
;; Vector read vlen/vlenb.
(define_insn_reservation "generic_ooo_vec_readlen" 4
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "rdvlenb,rdvl"))
"generic_ooo_vxu_issue,generic_ooo_vxu_issue")
;; Transfer from/to coprocessor. Assume not pipelined.
(define_insn_reservation "generic_ooo_xfer" 4
(and (eq_attr "tune" "generic_ooo")

143
gcc/config/riscv/generic-vector-ooo.md Normal file
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@ -0,0 +1,143 @@
;; Copyright (C) 2024-2024 Free Software Foundation, Inc.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Vector load/store
(define_automaton "vector_ooo")
;; Separate issue queue for vector instructions.
(define_cpu_unit "vxu_ooo_issue" "vector_ooo")
;; Vector execution unit.
(define_cpu_unit "vxu_ooo_alu" "vector_ooo")
;; Vector subunit that does mult/div/sqrt.
(define_cpu_unit "vxu_ooo_multicycle" "vector_ooo")
(define_insn_reservation "vec_load" 6
(eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr")
"vxu_ooo_issue,vxu_ooo_alu")
(define_insn_reservation "vec_store" 6
(eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector segment loads/stores.
(define_insn_reservation "vec_loadstore_seg" 10
(eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
vssegte,vssegts,vssegtux,vssegtox")
"vxu_ooo_issue,vxu_ooo_alu")
;; Regular vector operations and integer comparisons.
(define_insn_reservation "vec_alu" 3
(eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\
vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector float comparison, conversion etc.
(define_insn_reservation "vec_fcmp" 3
(eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\
vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
vfncvtftoi,vfncvtftof")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector integer multiplication.
(define_insn_reservation "vec_imul" 4
(eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\
vghsh,vgmul")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector float addition.
(define_insn_reservation "vec_fadd" 4
(eq_attr "type" "vfalu,vfwalu")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector float multiplication and FMA.
(define_insn_reservation "vec_fmul" 6
(eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector crypto, assumed to be a generic operation for now.
(define_insn_reservation "vec_crypto" 4
(eq_attr "type" "crypto")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector crypto, AES
(define_insn_reservation "vec_crypto_aes" 4
(eq_attr "type" "vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector crypto, sha
(define_insn_reservation "vec_crypto_sha" 4
(eq_attr "type" "vsha2ms,vsha2ch,vsha2cl")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector crypto, SM3/4
(define_insn_reservation "vec_crypto_sm" 4
(eq_attr "type" "vsm4k,vsm4r,vsm3me,vsm3c")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector permute.
(define_insn_reservation "vec_perm" 3
(eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\
vislide1down,vfslide1up,vfslide1down,vgather,vcompress")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector reduction.
(define_insn_reservation "vec_reduction" 8
(eq_attr "type" "vired,viwred,vfredu,vfwredu")
"vxu_ooo_issue,vxu_ooo_multicycle")
;; Vector ordered reduction, assume the latency number is for
;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost
;; for larger vectors.
(define_insn_reservation "vec_ordered_reduction" 10
(eq_attr "type" "vfredo,vfwredo")
"vxu_ooo_issue,vxu_ooo_multicycle*3")
;; Vector integer division, assume not pipelined.
(define_insn_reservation "vec_idiv" 16
(eq_attr "type" "vidiv")
"vxu_ooo_issue,vxu_ooo_multicycle*3")
;; Vector float divisions and sqrt, assume not pipelined.
(define_insn_reservation "vec_float_divsqrt" 16
(eq_attr "type" "vfdiv,vfsqrt")
"vxu_ooo_issue,vxu_ooo_multicycle*3")
;; Vector mask operations.
(define_insn_reservation "vec_mask" 2
(eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\
vfmovvf,vfmovfv")
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector vsetvl.
(define_insn_reservation "vec_vesetvl" 1
(eq_attr "type" "vsetvl,vsetvl_pre")
"vxu_ooo_issue")
;; Vector rounding mode setters, assume pipeline barrier.
(define_insn_reservation "vec_setrm" 20
(eq_attr "type" "wrvxrm,wrfrm")
"vxu_ooo_issue,vxu_ooo_issue*3")
;; Vector read vlen/vlenb.
(define_insn_reservation "vec_readlen" 4
(eq_attr "type" "rdvlenb,rdvl")
"vxu_ooo_issue,vxu_ooo_issue")

1
gcc/config/riscv/riscv.md
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@ -3851,6 +3851,7 @@
(include "sifive-p400.md")
(include "sifive-p600.md")
(include "thead.md")
(include "generic-vector-ooo.md")
(include "generic-ooo.md")
(include "vector.md")
(include "vector-crypto.md")