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pa-64.h: New file.

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* pa/pa-64.h: New file.
        * pa/pa64-regs.h: New file.
        * pa/pa64-start.h: New file.
        * pa/t-pa64: New file.
        * pa/xm-pa64hpux.h: New file.

From-SVN: r32898
This commit is contained in:
Jeffrey A Law 2000-04-04 06:42:40 +00:00 • committed by Jeff Law
parent e77d72cbc0
commit 6b940b3910
6 changed files with 786 additions and 0 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
Tue Apr 4 00:41:53 2000 Jeffrey A Law (law@cygnus.com)
* pa/pa-64.h: New file.
* pa/pa64-regs.h: New file.
* pa/pa64-start.h: New file.
* pa/t-pa64: New file.
* pa/xm-pa64hpux.h: New file.
2000-04-03 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* sparc.c (output_restore_regs): Prototype.

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gcc/config/pa/pa-64.h Normal file
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/* Definitions of target machine for GNU compiler, for HPs using the
64bit runtime model.
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* We can debug dynamically linked executables on hpux11; we also
want dereferencing of a NULL pointer to cause a SEGV. */
#undef LINK_SPEC
#define LINK_SPEC \
"-E %{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{shared:-shared}"
/* Like the default, except no -lg. */
#undef LIB_SPEC
#define LIB_SPEC \
"%{!shared:\
%{!p:\
%{!pg:\
%{!threads:-lc}\
%{threads:-lcma -lc_r}}\
%{p: -L/lib/libp/ -lc}\
%{pg: -L/lib/libp/ -lc}}} /usr/lib/pa20_64/milli.a"
/* Under hpux11, the normal location of the `ld' and `as' programs is the
/usr/ccs/bin directory. */
#ifndef CROSS_COMPILE
#undef MD_EXEC_PREFIX
#define MD_EXEC_PREFIX "/opt/langtools/bin"
#endif
/* Under hpux11 the normal location of the various *crt*.o files is the
/usr/ccs/lib directory. */
#ifndef CROSS_COMPILE
#undef MD_STARTFILE_PREFIX
#define MD_STARTFILE_PREFIX "/opt/langtools/lib/pa20_64/"
#endif
/* hpux11 has the new HP assembler. It's still lousy, but it's a whole lot
better than the assembler shipped with older versions of hpux. */
#define NEW_HP_ASSEMBLER
/* The default sizes for basic datatypes provided by GCC are not
correct for the PA64 runtime architecture.
In PA64, basic types have the following sizes
char 1 byte
short 2 bytes
int 4 bytes
long 8 bytes
long long 8 bytes
pointer 8 bytes
float 4 bytes
double 8 bytes
long double 16 bytes
size_t 8 bytes
ptrdiff_t 8 bytes
wchar 4 bytes
Make GCC agree with types.h. */
#undef SIZE_TYPE
#undef PTRDIFF_TYPE
#define SIZE_TYPE "long unsigned int"
#define PTRDIFF_TYPE "long int"
/* If it is not listed here, then the default selected by GCC is OK. */
#define SHORT_TYPE_SIZE 16
#define INT_TYPE_SIZE 32
#define MAX_LONG_TYPE_SIZE 64
#define LONG_TYPE_SIZE 64
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
/* This should be 128, but until we work out the ABI for the 128bit
FP codes supplied by HP we'll keep it at 64 bits. */
#undef LONG_DOUBLE_TYPE_SIZE
#define LONG_DOUBLE_TYPE_SIZE 64
#define MAX_WCHAR_TYPE_SIZE 32
#undef ASM_FILE_START
#define ASM_FILE_START(FILE) \
do { \
if (TARGET_64BIT) \
fputs("\t.LEVEL 2.0w\n", FILE); \
else if (TARGET_PA_11) \
fputs("\t.LEVEL 2.0\n", FILE); \
else if (TARGET_PA_11) \
fputs("\t.LEVEL 1.1\n", FILE); \
else \
fputs("\t.LEVEL 1.0\n", FILE); \
if (profile_flag)\
fprintf (FILE, "\t.IMPORT _mcount, CODE\n");\
if (write_symbols != NO_DEBUG) \
output_file_directive ((FILE), main_input_filename); \
} while (0)
/* Temporary until we figure out what to do with those *(&@$ 32bit
relocs which appear in stabs. */
#undef DBX_DEBUGGING_INFO
/* We want the compiler to select a suitable secondary memory location.
?!? This may not work reliably. Keep an eye out for problems. */
#undef SECONDARY_MEMORY_NEEDED_RTX
/* ?!? This needs to be made compile-time selectable.
The PA64 runtime model has arguments that grow to higher addresses
(like most other targets). The older runtime model has arguments
that grow to lower addresses. What fun. */
#undef ARGS_GROW_DOWNWARD
#undef ARG_POINTER_REGNUM
#define ARG_POINTER_REGNUM 29
#undef STATIC_CHAIN_REGNUM
#define STATIC_CHAIN_REGNUM 31
/* This is not needed for correct operation in 32bit mode, and since
older versions of gas and the hpux assembler do not accept .dword
we put this here instead of the more logical location, pa.h. */
#define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
{ fputs ("\t.dword ", FILE); \
if (function_label_operand (VALUE, VOIDmode)) \
fputs ("P%", FILE); \
output_addr_const (FILE, (VALUE)); \
fputs ("\n", FILE);}
/* It looks like DWARF2 will be the easiest debug format to handle on this
platform. */
#define OBJECT_FORMAT_ELF
#define DWARF2_DEBUGGING_INFO
#define PREFERRED_DEBUGGING_FORMAT DWARF2_DEBUG
/* This isn't quite ready yet. I'm seeing it mess up some line
tables. For example, we're getting lines starting/ending at
impossible addresses. */
#define DWARF2_ASM_LINE_DEBUG_INFO 1
/* Nonzero if we do not know how to pass TYPE solely in registers. */
#define MUST_PASS_IN_STACK(MODE,TYPE) \
((TYPE) != 0 \
&& (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
|| TREE_ADDRESSABLE (TYPE)))
/* The rest of this file is copied from the generic svr4.h. One day we
would like to simply include svr4.h instead of copying all these
definitions. */
/* Support const sections and the ctors and dtors sections for g++.
Note that there appears to be two different ways to support const
sections at the moment. You can either #define the symbol
READONLY_DATA_SECTION (giving it some code which switches to the
readonly data section) or else you can #define the symbols
EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
SELECT_RTX_SECTION. We do both here just to be on the safe side. */
#define USE_CONST_SECTION 1
#define CONST_SECTION_ASM_OP "\t.section\t.rodata"
/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
Note that we want to give these sections the SHF_WRITE attribute
because these sections will actually contain data (i.e. tables of
addresses of functions in the current root executable or shared library
file) and, in the case of a shared library, the relocatable addresses
will have to be properly resolved/relocated (and then written into) by
the dynamic linker when it actually attaches the given shared library
to the executing process. (Note that on SVR4, you may wish to use the
`-z text' option to the ELF linker, when building a shared library, as
an additional check that you are doing everything right. But if you do
use the `-z text' option when building a shared library, you will get
errors unless the .ctors and .dtors sections are marked as writable
via the SHF_WRITE attribute.) */
#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\""
#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\""
/* On svr4, we *do* have support for the .init and .fini sections, and we
can put stuff in there to be executed before and after `main'. We let
crtstuff.c and other files know this by defining the following symbols.
The definitions say how to change sections to the .init and .fini
sections. This is the same for all known svr4 assemblers. */
/* ??? For the time being, we aren't using init sections. */
#if 0
#define INIT_SECTION_ASM_OP "\t.section\t.init"
#define FINI_SECTION_ASM_OP "\t.section\t.fini"
#endif
/* A default list of other sections which we might be "in" at any given
time. For targets that use additional sections (e.g. .tdesc) you
should override this definition in the target-specific file which
includes this file. */
#undef EXTRA_SECTIONS
#define EXTRA_SECTIONS in_const, in_ctors, in_dtors
/* A default list of extra section function definitions. For targets
that use additional sections (e.g. .tdesc) you should override this
definition in the target-specific file which includes this file. */
#undef EXTRA_SECTION_FUNCTIONS
#define EXTRA_SECTION_FUNCTIONS \
CONST_SECTION_FUNCTION \
CTORS_SECTION_FUNCTION \
DTORS_SECTION_FUNCTION
#define READONLY_DATA_SECTION() const_section ()
extern void text_section ();
#define CONST_SECTION_FUNCTION \
void \
const_section () \
{ \
if (!USE_CONST_SECTION) \
text_section(); \
else if (in_section != in_const) \
{ \
fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP); \
in_section = in_const; \
} \
}
#define CTORS_SECTION_FUNCTION \
void \
ctors_section () \
{ \
if (in_section != in_ctors) \
{ \
fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
in_section = in_ctors; \
} \
}
#define DTORS_SECTION_FUNCTION \
void \
dtors_section () \
{ \
if (in_section != in_dtors) \
{ \
fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
in_section = in_dtors; \
} \
}
/* Switch into a generic section.
We make the section read-only and executable for a function decl,
read-only for a const data decl, and writable for a non-const data decl.
If the section has already been defined, we must not
emit the attributes here. The SVR4 assembler does not
recognize section redefinitions.
If DECL is NULL, no attributes are emitted. */
#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
do { \
static struct section_info \
{ \
struct section_info *next; \
char *name; \
enum sect_enum {SECT_RW, SECT_RO, SECT_EXEC} type; \
} *sections; \
struct section_info *s; \
char *mode; \
enum sect_enum type; \
\
for (s = sections; s; s = s->next) \
if (!strcmp (NAME, s->name)) \
break; \
\
if (DECL && TREE_CODE (DECL) == FUNCTION_DECL) \
type = SECT_EXEC, mode = "ax"; \
else if (DECL && DECL_READONLY_SECTION (DECL, RELOC)) \
type = SECT_RO, mode = "a"; \
else \
type = SECT_RW, mode = "aw"; \
\
if (s == 0) \
{ \
s = (struct section_info *) xmalloc (sizeof (struct section_info)); \
s->name = xmalloc ((strlen (NAME) + 1) * sizeof (*NAME)); \
strcpy (s->name, NAME); \
s->type = type; \
s->next = sections; \
sections = s; \
fprintf (FILE, "\t.section\t%s,\"%s\",@progbits\n", NAME, mode); \
} \
else \
{ \
if (DECL && s->type != type) \
error_with_decl (DECL, "%s causes a section type conflict"); \
\
fprintf (FILE, "\t.section\t%s\n", NAME); \
} \
} while (0)
#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
#define UNIQUE_SECTION(DECL,RELOC) \
do { \
int len; \
char *name, *string, *prefix; \
\
name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL)); \
\
if (! DECL_ONE_ONLY (DECL)) \
{ \
prefix = "."; \
if (TREE_CODE (DECL) == FUNCTION_DECL) \
prefix = ".text."; \
else if (DECL_READONLY_SECTION (DECL, RELOC)) \
prefix = ".rodata."; \
else \
prefix = ".data."; \
} \
else if (TREE_CODE (DECL) == FUNCTION_DECL) \
prefix = ".gnu.linkonce.t."; \
else if (DECL_READONLY_SECTION (DECL, RELOC)) \
prefix = ".gnu.linkonce.r."; \
else \
prefix = ".gnu.linkonce.d."; \
\
len = strlen (name) + strlen (prefix); \
string = alloca (len + 1); \
sprintf (string, "%s%s", prefix, name); \
\
DECL_SECTION_NAME (DECL) = build_string (len, string); \
} while (0)
#define INT_ASM_OP ".dword"
/* A C statement (sans semicolon) to output an element in the table of
global constructors. */
#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
do { \
ctors_section (); \
fprintf (FILE, "\t%s\t P%%", INT_ASM_OP); \
assemble_name (FILE, NAME); \
fprintf (FILE, "\n"); \
} while (0)
/* A C statement (sans semicolon) to output an element in the table of
global destructors. */
#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
do { \
dtors_section (); \
fprintf (FILE, "\t%s\t P%%", INT_ASM_OP); \
assemble_name (FILE, NAME); \
fprintf (FILE, "\n"); \
} while (0)
/* ??? For the time being, we aren't using .ctors/.dtors sections. */
#undef ASM_OUTPUT_DESTRUCTOR
#undef ASM_OUTPUT_CONSTRUCTOR
/* Define the strings used for the special svr4 .type and .size directives.
These strings generally do not vary from one system running svr4 to
another, but if a given system (e.g. m88k running svr) needs to use
different pseudo-op names for these, they may be overridden in the
file which includes this one. */
#define TYPE_ASM_OP ".type"
#define SIZE_ASM_OP ".size"
/* This is how we tell the assembler that a symbol is weak. */
#define ASM_WEAKEN_LABEL(FILE,NAME) \
do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
fputc ('\n', FILE); } while (0)
/* The following macro defines the format used to output the second
operand of the .type assembler directive. Different svr4 assemblers
expect various different forms for this operand. The one given here
is just a default. You may need to override it in your machine-
specific tm.h file (depending upon the particulars of your assembler). */
#define TYPE_OPERAND_FMT "@%s"
/* Write the extra assembler code needed to declare a function's result.
Most svr4 assemblers don't require any special declaration of the
result value, but there are exceptions. */
#ifndef ASM_DECLARE_RESULT
#define ASM_DECLARE_RESULT(FILE, RESULT)
#endif

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/* Configuration for GNU C-compiler for PA-RISC.
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* Standard register usage.
It is safe to refer to actual register numbers in this file. */
/* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler
from 0 to just below FIRST_PSEUDO_REGISTER.
All registers that the compiler knows about must be given numbers,
even those that are not normally considered general registers.
HP-PA 2.0w has 32 fullword registers and 32 floating point
registers. However, the floating point registers behave
differently: the left and right halves of registers are addressable
as 32 bit registers.
Due to limitations within GCC itself, we do not expose the left/right
half addressability when in wide mode. This is not a major performance
issue as using the halves independently triggers false dependency stalls
anyway. */
#define FIRST_PSEUDO_REGISTER 61 /* 32 general regs + 28 fp regs +
+ 1 shift reg */
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator.
On the HP-PA, these are:
Reg 0 = 0 (hardware). However, 0 is used for condition code,
so is not fixed.
Reg 1 = ADDIL target/Temporary (hardware).
Reg 2 = Return Pointer
Reg 3 = Frame Pointer
Reg 4 = Frame Pointer (>8k varying frame with HP compilers only)
Reg 4-18 = Preserved Registers
Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme.
Reg 20-22 = Temporary Registers
Reg 23-26 = Temporary/Parameter Registers
Reg 27 = Global Data Pointer (hp)
Reg 28 = Temporary/???/Return Value register
Reg 29 = Temporary/Static Chain/Return Value register #2
Reg 30 = stack pointer
Reg 31 = Temporary/Millicode Return Pointer (hp)
Freg 0-3 = Status Registers -- Not known to the compiler.
Freg 4-7 = Arguments/Return Value
Freg 8-11 = Temporary Registers
Freg 12-21 = Preserved Registers
Freg 22-31 = Temporary Registers
*/
#define FIXED_REGISTERS \
{0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 1, 0, \
/* fp registers */ \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, \
/* shift register */ \
0}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
registers that can be used without being saved.
The latter must include the registers where values are returned
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like. */
#define CALL_USED_REGISTERS \
{1, 1, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, \
/* fp registers */ \
1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, \
/* shift register */ \
1}
#define CONDITIONAL_REGISTER_USAGE \
{ \
if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
{ \
for (i = FP_REG_FIRST; i < FP_REG_LAST; i++)\
fixed_regs[i] = call_used_regs[i] = 1; \
} \
if (flag_pic) \
{ \
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
fixed_regs[PIC_OFFSET_TABLE_REGNUM_SAVED] = 1;\
} \
}
/* Allocate the call used registers first. This should minimize
the number of registers that need to be saved (as call used
registers will generally not be allocated across a call).
Experimentation has shown slightly better results by allocating
FP registers first.
FP registers are ordered so that all L registers are selected before
R registers. This works around a false dependency interlock on the
PA8000 when accessing the high and low parts of an FP register
independently. */
#define REG_ALLOC_ORDER \
{ \
/* caller-saved fp regs. */ \
50, 51, 52, 53, 54, 55, 56, 57, \
58, 59, 36, 37, 38, 39, 32, 33, \
34, 35, \
/* caller-saved general regs. */ \
19, 20, 21, 22, 23, 24, 25, 26, \
27, 28, 29, 31, 2, \
/* callee-saved fp regs. */ \
40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, \
/* callee-saved general regs. */ \
3, 4, 5, 6, 7, 8, 9, 10, \
11, 12, 13, 14, 15, 16, 17, 18, \
/* special registers. */ \
1, 30, 0, 60}
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
This is ordinarily the length in words of a value of mode MODE
but can be less for certain modes in special long registers.
For PA64, GPRs and FPRs hold 64 bits worth (we ignore the 32bit
addressability of the FPRs). ie, we pretend each register holds
precisely WORD_SIZE bits. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
On the HP-PA, the cpu registers can hold any mode. We
force this to be an even register is it cannot hold the full mode. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO) == 0 \
? (MODE) == CCmode || (MODE) == CCFPmode \
/* Make wide modes be in aligned registers. */ \
: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
|| GET_MODE_SIZE (MODE) <= 2 * UNITS_PER_WORD && ((REGNO) & 1) == 0))
/* How to renumber registers for dbx and gdb.
Registers 0 - 31 remain unchanged.
Registers 32 - 60 are mapped to 72, 74, 76 ...
Register 88 is mapped to 32. */
#define DBX_REGISTER_NUMBER(REGNO) \
((REGNO) <= 31 ? (REGNO) : \
((REGNO) > 31 && (REGNO) <= 60 ? (REGNO - 32) * 2 + 72 : 32))
/* Define the classes of registers for register constraints in the
machine description. Also define ranges of constants.
One of the classes must always be named ALL_REGS and include all hard regs.
If there is more than one class, another class must be named NO_REGS
and contain no registers.
The name GENERAL_REGS must be the name of a class (or an alias for
another name such as ALL_REGS). This is the class of registers
that is allowed by "g" or "r" in a register constraint.
Also, registers outside this class are allocated only when
instructions express preferences for them.
The classes must be numbered in nondecreasing order; that is,
a larger-numbered class must never be contained completely
in a smaller-numbered class.
For any two classes, it is very desirable that there be another
class that represents their union. */
/* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
1.1 fp regs, and the high 1.1 fp regs, to which the operands of
fmpyadd and fmpysub are restricted. */
enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
"GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. Register 0, the "condition code" register,
is in no class. */
#define REG_CLASS_CONTENTS \
{{0x00000000, 0x00000000}, /* NO_REGS */ \
{0x00000002, 0x00000000}, /* R1_REGS */ \
{0xfffffffe, 0x00000000}, /* GENERAL_REGS */ \
{0x00000000, 0x00000000}, /* FPUPPER_REGS */ \
{0x00000000, 0x0fffffff}, /* FP_REGS */ \
{0xfffffffe, 0x0fffffff}, /* GENERAL_OR_FP_REGS */ \
{0x00000000, 0x10000000}, /* SHIFT_REGS */ \
{0xfffffffe, 0x1fffffff}} /* ALL_REGS */
/* This may not actually be necessary anymore. But until I can prove
otherwise it will stay. */
#define CLASS_CANNOT_CHANGE_SIZE (FP_REGS)
/* The same information, inverted:
Return the class number of the smallest class containing
reg number REGNO. This could be a conditional expression
or could index an array. */
#define REGNO_REG_CLASS(REGNO) \
((REGNO) == 0 ? NO_REGS \
: (REGNO) == 1 ? R1_REGS \
: (REGNO) < 32 ? GENERAL_REGS \
: (REGNO) < 60 ? FP_REGS \
: SHIFT_REGS)
/* Get reg_class from a letter such as appears in the machine description. */
/* Keep 'x' for backward compatibility with user asm. */
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'f' ? FP_REGS : \
(C) == 'y' ? FP_REGS : \
(C) == 'x' ? FP_REGS : \
(C) == 'q' ? SHIFT_REGS : \
(C) == 'a' ? R1_REGS : \
(C) == 'Z' ? ALL_REGS : NO_REGS)
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
#define CLASS_MAX_NREGS(CLASS, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* 1 if N is a possible register number for function argument passing. */
#define FUNCTION_ARG_REGNO_P(N) \
((((N) >= 19) && (N) <= 26) \
|| (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
/* How to refer to registers in assembler output.
This sequence is indexed by compiler's hard-register-number (see above). */
#define REGISTER_NAMES \
{"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
"%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \
"%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \
"%fr4", "%fr5", "%fr6", "%fr7", "%fr8", "%fr9", "%fr10", "%fr11", \
"%fr12", "%fr13", "%fr14", "%fr15", "%fr16", "%fr17", "%fr18", "%fr19", \
"%fr20", "%fr21", "%fr22", "%fr23", "%fr24", "%fr25", "%fr26", "%fr27", \
"%fr28", "%fr29", "%fr30", "%fr31", "SAR"}
#define ADDITIONAL_REGISTER_NAMES \
{{"%cr11",88}}
#define FP_SAVED_REG_LAST 49
#define FP_SAVED_REG_FIRST 40
#define FP_REG_STEP 1
#define FP_REG_FIRST 32
#define FP_REG_LAST 59

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/* It is currently impossible to switch between PA32 and PA64 based on a
runtime compiler switch. So we might as well lose the overhead with
checking for TARGET_64BIT. */
#define TARGET_64BIT 1
#define TARGET_PA_11 1
#defien TARGET_PA_20 1

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LIBGCC1=libgcc1.null
CROSS_LIBGCC1=libgcc1.null
ADA_CFLAGS=-mdisable-indexing
LIB2FUNCS_EXTRA=quadlib.c
TARGET_LIBGCC2_CFLAGS = -fPIC
# We'll need this once .init sections are enabled on PA64.
#EXTRA_PARTS = crtbegin.o crtend.o
# For the time being, we are using collect.
#USE_COLLECT2 =
quadlib.c: $(srcdir)/config/pa/quadlib.c
rm -f quadlib.c
cp $(srcdir)/config/pa/quadlib.c .

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/* Configuration for GNU C-compiler for PA-RISC.
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* HP-UX is a flavor of System V */
#define USG
/* Use System V memory functions. */
/* #defines that need visibility everywhere. */
#define FALSE 0
#define TRUE 1
/* This describes the machine the compiler is hosted on. */
#define HOST_BITS_PER_CHAR 8
#define HOST_BITS_PER_SHORT 16
#define HOST_BITS_PER_INT 32
#define HOST_BITS_PER_LONG 64
#define HOST_BITS_PER_LONGLONG 64
/* Doubles are stored in memory with the high order word first. This
matters when cross-compiling. */
#define HOST_WORDS_BIG_ENDIAN 1
/* Place any machine-dependent include files here, in case we
are bootstrapping. */
/* target machine dependencies.
tm.h is a symbolic link to the actual target specific file. */
#include "tm.h"
/* Arguments to use with `exit'. */
#define SUCCESS_EXIT_CODE 0
#define FATAL_EXIT_CODE 33
/* Don't try to use sys_siglist. */
#define NO_SYS_SIGLIST
/* HP's compiler has problems with enum bitfields. */
#define ONLY_INT_FIELDS
/* Always claim to use C alloca; this prevents losing if building with
gcc -fno-builtin ... */
#define USE_C_ALLOCA