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i386.c (expand_vec_perm_1): Fix expand_vec_perm_palignr case.

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* config/i386/i386.c (expand_vec_perm_1): Fix
	expand_vec_perm_palignr case.
	* config/i386/sse.md (<ssse3_avx2>_palignr<mode>_mask): Use
	VI1_AVX512.

From-SVN: r216504
This commit is contained in:
Ilya Tocar 2014-10-21 09:51:49 +00:00 • committed by Jakub Jelinek
parent 0f01f7406b
commit 6afcac3243
3 changed files with 14 additions and 6 deletions
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7
gcc/ChangeLog
View file

@ -1,3 +1,10 @@
2014-10-21 Ilya Tocar <ilya.tocar@intel.com>
* config/i386/i386.c (expand_vec_perm_1): Fix
expand_vec_perm_palignr case.
* config/i386/sse.md (<ssse3_avx2>_palignr<mode>_mask): Use
VI1_AVX512.
2014-10-21 Zhenqiang Chen <zhenqiang.chen@arm.com>
* cfgloopanal.c (seq_cost): Delete.

1
gcc/config/i386/i386.c
View file

@ -43552,6 +43552,7 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d)
/* Try the AVX2 vpalignr instruction. */
if (expand_vec_perm_palignr (d, true))
return true;
/* Try the AVX512F vpermi2 instructions. */
if (ix86_expand_vec_perm_vpermi2 (NULL_RTX, NULL_RTX, NULL_RTX, NULL_RTX, d))

12
gcc/config/i386/sse.md
View file

@ -13716,14 +13716,14 @@
(set_attr "mode" "DI")])
(define_insn "<ssse3_avx2>_palignr<mode>_mask"
[(set (match_operand:VI1_AVX2 0 "register_operand" "=v")
(vec_merge:VI1_AVX2
(unspec:VI1_AVX2
[(match_operand:VI1_AVX2 1 "register_operand" "v")
(match_operand:VI1_AVX2 2 "nonimmediate_operand" "vm")
[(set (match_operand:VI1_AVX512 0 "register_operand" "=v")
(vec_merge:VI1_AVX512
(unspec:VI1_AVX512
[(match_operand:VI1_AVX512 1 "register_operand" "v")
(match_operand:VI1_AVX512 2 "nonimmediate_operand" "vm")
(match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
UNSPEC_PALIGNR)
(match_operand:VI1_AVX2 4 "vector_move_operand" "0C")
(match_operand:VI1_AVX512 4 "vector_move_operand" "0C")
(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
"TARGET_AVX512BW && (<MODE_SIZE> == 64 || TARGET_AVX512VL)"
{