rs6000: Comment fixes + some leftovers
* config/rs6000/rs6000.c: Update all comments that mentioned SPE. (rs6000_expand_builtin): Remove RS6000_BTC_EVSEL. * config/rs6000/rs6000.h (RS6000_BTC_EVSEL): Delete. * config/rs6000/vxworks.h (VXCPU_FOR_8548): Delete. Adjust former use. * config/rs6000/vxworksae.h (VXCPU_FOR_8548): Delete. * config/rs6000/vxworksmils.h (VXCPU_FOR_8548): Delete. From-SVN: r249170
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
d20ae4d7da
commit
6ae036b330
6 changed files with 42 additions and 67 deletions
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@ -1,3 +1,12 @@
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2017-06-13 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.c: Update all comments that mentioned SPE.
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(rs6000_expand_builtin): Remove RS6000_BTC_EVSEL.
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* config/rs6000/rs6000.h (RS6000_BTC_EVSEL): Delete.
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* config/rs6000/vxworks.h (VXCPU_FOR_8548): Delete. Adjust former use.
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* config/rs6000/vxworksae.h (VXCPU_FOR_8548): Delete.
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* config/rs6000/vxworksmils.h (VXCPU_FOR_8548): Delete.
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2017-06-13 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000-opts.h (enum rs6000_vector): Delete VECTOR_SPE.
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@ -2014,10 +2014,6 @@ rs6000_cpu_name_lookup (const char *name)
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This is ordinarily the length in words of a value of mode MODE
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but can be less for certain modes in special long registers.
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For the SPE, GPRs are 64 bits but only 32 bits are visible in
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scalar instructions. The upper 32 bits are only available to the
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SIMD instructions.
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POWER and PowerPC GPRs hold 32 bits worth;
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PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
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@ -2901,9 +2897,7 @@ rs6000_setup_reg_addr_masks (void)
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addr_mask |= RELOAD_REG_INDEXED;
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/* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
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addressing. Restrict addressing on SPE for 64-bit types
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because of the SUBREG hackery used to address 64-bit floats in
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'32-bit' GPRs. If we allow scalars into Altivec registers,
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addressing. If we allow scalars into Altivec registers,
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don't allow PRE_INC, PRE_DEC, or PRE_MODIFY. */
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if (TARGET_UPDATE
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@ -3171,7 +3165,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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rs6000_vector_align[TImode] = align64;
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}
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/* TODO add SPE and paired floating point vector support. */
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/* TODO add paired floating point vector support. */
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/* Register class constraints for the constraints that depend on compile
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switches. When the VSX code was added, different constraints were added
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@ -3827,8 +3821,7 @@ darwin_rs6000_override_options (void)
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/* Return the builtin mask of the various options used that could affect which
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builtins were used. In the past we used target_flags, but we've run out of
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bits, and some options like SPE and PAIRED are no longer in
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target_flags. */
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bits, and some options like PAIRED are no longer in target_flags. */
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HOST_WIDE_INT
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rs6000_builtin_mask_calculate (void)
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@ -5479,8 +5472,7 @@ rs6000_option_override_internal (bool global_init_p)
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/* Set the builtin mask of the various options used that could affect which
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builtins were used. In the past we used target_flags, but we've run out
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of bits, and some options like SPE and PAIRED are no longer in
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target_flags. */
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of bits, and some options like PAIRED are no longer in target_flags. */
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rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
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if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
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rs6000_print_builtin_options (stderr, 0, "builtin mask",
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@ -11767,7 +11759,6 @@ function_arg_padding (machine_mode mode, const_tree type)
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However, we're stuck with this because changing the ABI might break
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existing library interfaces.
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Doubleword align SPE vectors.
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Quadword align Altivec/VSX vectors.
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Quadword align large synthetic vector types. */
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@ -12188,18 +12179,17 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
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int n_words = rs6000_arg_size (mode, type);
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int gregno = cum->sysv_gregno;
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/* Long long and SPE vectors are put in (r3,r4), (r5,r6),
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(r7,r8) or (r9,r10). As does any other 2 word item such
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as complex int due to a historical mistake. */
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/* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
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As does any other 2 word item such as complex int due to a
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historical mistake. */
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if (n_words == 2)
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gregno += (1 - gregno) & 1;
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/* Multi-reg args are not split between registers and stack. */
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if (gregno + n_words - 1 > GP_ARG_MAX_REG)
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{
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/* Long long and SPE vectors are aligned on the stack.
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So are other 2 word items such as complex int due to
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a historical mistake. */
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/* Long long is aligned on the stack. So are other 2 word
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items such as complex int due to a historical mistake. */
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if (n_words == 2)
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cum->words += cum->words & 1;
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cum->words += n_words;
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@ -12736,9 +12726,9 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
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int n_words = rs6000_arg_size (mode, type);
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int gregno = cum->sysv_gregno;
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/* Long long and SPE vectors are put in (r3,r4), (r5,r6),
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(r7,r8) or (r9,r10). As does any other 2 word item such
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as complex int due to a historical mistake. */
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/* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
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As does any other 2 word item such as complex int due to a
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historical mistake. */
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if (n_words == 2)
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gregno += (1 - gregno) & 1;
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@ -13675,9 +13665,8 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
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lab_false = create_artificial_label (input_location);
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lab_over = create_artificial_label (input_location);
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/* Long long and SPE vectors are aligned in the registers.
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As are any other 2 gpr item such as complex int due to a
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historical mistake. */
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/* Long long is aligned in the registers. As are any other 2 gpr
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item such as complex int due to a historical mistake. */
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u = reg;
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if (n_reg == 2 && reg == gpr)
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{
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@ -16623,7 +16612,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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case RS6000_BTC_TERNARY: name3 = "ternary"; break;
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case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
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case RS6000_BTC_ABS: name3 = "abs"; break;
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case RS6000_BTC_EVSEL: name3 = "evsel"; break;
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case RS6000_BTC_DST: name3 = "dst"; break;
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}
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@ -17011,11 +16999,11 @@ rs6000_init_builtins (void)
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pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
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pixel_type_node, 8);
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/* Paired and SPE builtins are only available if you build a compiler with
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the appropriate options, so only create those builtins with the
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appropriate compiler option. Create Altivec and VSX builtins on machines
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with at least the general purpose extensions (970 and newer) to allow the
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use of the target attribute. */
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/* Paired builtins are only available if you build a compiler with the
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appropriate options, so only create those builtins with the appropriate
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compiler option. Create Altivec and VSX builtins on machines with at
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least the general purpose extensions (970 and newer) to allow the use of
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the target attribute. */
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if (TARGET_PAIRED_FLOAT)
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paired_init_builtins ();
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if (TARGET_EXTRA_BUILTINS)
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@ -18147,11 +18135,11 @@ rs6000_common_init_builtins (void)
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builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
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}
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/* Paired and SPE builtins are only available if you build a compiler with
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the appropriate options, so only create those builtins with the
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appropriate compiler option. Create Altivec and VSX builtins on machines
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with at least the general purpose extensions (970 and newer) to allow the
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use of the target attribute.. */
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/* Paired builtins are only available if you build a compiler with the
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appropriate options, so only create those builtins with the appropriate
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compiler option. Create Altivec and VSX builtins on machines with at
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least the general purpose extensions (970 and newer) to allow the use of
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the target attribute.. */
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if (TARGET_EXTRA_BUILTINS)
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builtin_mask |= RS6000_BTM_COMMON;
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@ -18395,7 +18383,7 @@ rs6000_common_init_builtins (void)
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mode0 = insn_data[icode].operand[0].mode;
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if (mode0 == V2SImode)
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{
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/* code for SPE */
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/* code for paired single */
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if (! (type = v2si_ftype))
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{
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v2si_ftype
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@ -23109,7 +23097,7 @@ print_operand (FILE *file, rtx x, int code)
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}
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return;
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/* Print AltiVec or SPE memory operand. */
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/* Print AltiVec memory operand. */
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case 'y':
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{
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rtx tmp;
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@ -26155,10 +26143,6 @@ rs6000_savres_strategy (rs6000_stack_t *info,
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+---------------------------------------+
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| Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
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+---------------------------------------+
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| SPE: area for 64-bit GP registers |
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+---------------------------------------+
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| SPE alignment padding |
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+---------------------------------------+
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| saved CR (C) | 8+P+A+V+L+X+W+Y+Z
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+---------------------------------------+
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| Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
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@ -29956,7 +29940,6 @@ rs6000_emit_epilogue (int sibcall)
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if (regno == INVALID_REGNUM)
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break;
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/* Note: possible use of r0 here to address SPE regs. */
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mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
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info->ehrd_offset + frame_off
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+ reg_size * (int) i);
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@ -36986,7 +36969,7 @@ altivec_expand_vec_perm_const (rtx operands[4])
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return false;
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}
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/* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
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/* Expand a Paired Single or VSX Permute Doubleword constant permutation.
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Return true if we match an efficient implementation. */
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static bool
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@ -37213,10 +37196,8 @@ rs6000_parallel_return (machine_mode mode,
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/* Target hook for TARGET_FUNCTION_VALUE.
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On the SPE, both FPs and vectors are returned in r3.
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On RS/6000 an integer value is in r3 and a floating-point value is in
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fp1, unless -msoft-float. */
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An integer value is in r3 and a floating-point value is in fp1,
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unless -msoft-float. */
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static rtx
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rs6000_function_value (const_tree valtype,
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@ -37428,7 +37409,7 @@ rs6000_initial_elimination_offset (int from, int to)
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return offset;
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}
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/* Fill in sizes for SPE register high parts in table used by unwinder. */
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/* Fill in sizes of registers used by unwinder. */
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static void
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rs6000_init_dwarf_reg_sizes_extra (tree address)
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@ -698,8 +698,8 @@ extern int rs6000_vector_align[];
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/* For power systems, we want to enable Altivec and VSX builtins even if the
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user did not use -maltivec or -mvsx to allow the builtins to be used inside
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of #pragma GCC target or the target attribute to change the code level for a
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given system. The SPE and Paired builtins are only enabled if you configure
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the compiler for those builtins, and those machines don't support altivec or
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given system. The Paired builtins are only enabled if you configure the
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compiler for those builtins, and those machines don't support altivec or
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VSX. */
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#define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \
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@ -2553,7 +2553,6 @@ extern int frame_pointer_needed;
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#define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */
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#define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */
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#define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */
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#define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */
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#define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */
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#define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
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@ -60,12 +60,6 @@ along with GCC; see the file COPYING3. If not see
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#define SUBTARGET_EXTRA_SPECS /* none needed */
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/* VxWorks and VxWorksAE (aka 653) expect different CPU values to designate
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SPE on 8548. We define a dedicated macro for the base VxWorks here, which
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the AE configuration will override. */
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#define VXCPU_FOR_8548 "PPC85XX"
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/* FIXME: The only reason we allow no -mcpu switch at all is because
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config-ml.in insists on a "." multilib. */
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#define CPP_SPEC \
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@ -79,7 +73,7 @@ along with GCC; see the file COPYING3. If not see
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mcpu=604 : -DCPU=PPC604 ; \
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mcpu=860 : -DCPU=PPC860 ; \
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mcpu=8540: -DCPU=PPC85XX ; \
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mcpu=8548: -DCPU=" VXCPU_FOR_8548 "; \
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mcpu=8548: -DCPU=PPC85XX ; \
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: -DCPU=PPC604 }}" \
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VXWORKS_ADDITIONAL_CPP_SPEC
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@ -18,10 +18,6 @@ You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* VxWorksAE for E500V2 expects a specific CPU value to designate 8548. */
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#undef VXCPU_FOR_8548
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#define VXCPU_FOR_8548 "PPCE500V2"
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/* This platform supports the probing method of stack checking and
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requires 4K of space for executing a possible last chance handler. */
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#undef STACK_CHECK_PROTECT
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@ -23,7 +23,3 @@ along with GCC; see the file COPYING3. If not see
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requires 4K of space for executing a possible last chance handler. */
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#undef STACK_CHECK_PROTECT
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#define STACK_CHECK_PROTECT 4096
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/* VxWorksMILS for E500V2 expects a specific CPU value to designate 8548. */
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#undef VXCPU_FOR_8548
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#define VXCPU_FOR_8548 "PPC85XX"
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