From 69c553ef2aa52adbaeab79751c1d421cc61f5216 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Mon, 11 Jun 2007 12:13:00 +0200 Subject: [PATCH] re PR target/32280 (_mm_srli_si128, heinous code for some shifts) PR target/32280 * config/i386/sse.md ("sse2_ashlti", "sse2_lshrti3"): Move ... * config/i386/i386.md ("sse2_ashlti", "sse2_lshrti3"): ... to here. testsuite/ChangeLog: PR target/32280 * gcc.target/i386/pr32280.c: New test. From-SVN: r125615 --- gcc/ChangeLog | 6 +++++ gcc/config/i386/i386.md | 32 +++++++++++++++++++++++++ gcc/config/i386/sse.md | 26 -------------------- gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/gcc.target/i386/pr32280.c | 17 +++++++++++++ 5 files changed, 60 insertions(+), 26 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr32280.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a026ca1d3c3..94067fc74e1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2007-06-11 Uros Bizjak + + PR target/32280 + * config/i386/sse.md ("sse2_ashlti", "sse2_lshrti3"): Move ... + * config/i386/i386.md ("sse2_ashlti", "sse2_lshrti3"): ... to here. + 2007-06-11 Uros Bizjak PR middle-end/32279 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 641b6a1692d..1a4733b4da1 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10317,6 +10317,22 @@ "#" [(set_attr "type" "multi")]) +;; This pattern must be defined before *ashlti3_2 to prevent +;; combine pass from converting sse2_ashlti3 to *ashlti3_2. + +(define_insn "sse2_ashlti3" + [(set (match_operand:TI 0 "register_operand" "=x") + (ashift:TI (match_operand:TI 1 "register_operand" "0") + (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] + "TARGET_SSE2" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) / 8); + return "pslldq\t{%2, %0|%0, %2}"; +} + [(set_attr "type" "sseishft") + (set_attr "prefix_data16" "1") + (set_attr "mode" "TI")]) + (define_insn "*ashlti3_2" [(set (match_operand:TI 0 "register_operand" "=r") (ashift:TI (match_operand:TI 1 "register_operand" "0") @@ -11990,6 +12006,22 @@ "#" [(set_attr "type" "multi")]) +;; This pattern must be defined before *lshrti3_2 to prevent +;; combine pass from converting sse2_lshrti3 to *lshrti3_2. + +(define_insn "sse2_lshrti3" + [(set (match_operand:TI 0 "register_operand" "=x") + (lshiftrt:TI (match_operand:TI 1 "register_operand" "0") + (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] + "TARGET_SSE2" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) / 8); + return "psrldq\t{%2, %0|%0, %2}"; +} + [(set_attr "type" "sseishft") + (set_attr "prefix_data16" "1") + (set_attr "mode" "TI")]) + (define_insn "*lshrti3_2" [(set (match_operand:TI 0 "register_operand" "=r") (lshiftrt:TI (match_operand:TI 1 "register_operand" "0") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a7a56490cab..2a4606fffe0 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3345,19 +3345,6 @@ (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) -(define_insn "sse2_ashlti3" - [(set (match_operand:TI 0 "register_operand" "=x") - (ashift:TI (match_operand:TI 1 "register_operand" "0") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] - "TARGET_SSE2" -{ - operands[2] = GEN_INT (INTVAL (operands[2]) / 8); - return "pslldq\t{%2, %0|%0, %2}"; -} - [(set_attr "type" "sseishft") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - (define_expand "vec_shl_" [(set (match_operand:SSEMODEI 0 "register_operand" "") (ashift:TI (match_operand:SSEMODEI 1 "register_operand" "") @@ -3370,19 +3357,6 @@ operands[1] = gen_lowpart (TImode, operands[1]); }) -(define_insn "sse2_lshrti3" - [(set (match_operand:TI 0 "register_operand" "=x") - (lshiftrt:TI (match_operand:TI 1 "register_operand" "0") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] - "TARGET_SSE2" -{ - operands[2] = GEN_INT (INTVAL (operands[2]) / 8); - return "psrldq\t{%2, %0|%0, %2}"; -} - [(set_attr "type" "sseishft") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - (define_expand "vec_shr_" [(set (match_operand:SSEMODEI 0 "register_operand" "") (lshiftrt:TI (match_operand:SSEMODEI 1 "register_operand" "") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f7d76fa848e..6c52a1d3d0e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2007-06-11 Uros Bizjak + + PR target/32280 + * gcc.target/i386/pr32280.c: New test. + 2007-06-11 Uros Bizjak PR middle-end/32279 diff --git a/gcc/testsuite/gcc.target/i386/pr32280.c b/gcc/testsuite/gcc.target/i386/pr32280.c new file mode 100644 index 00000000000..e6377e6451c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr32280.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ +/* { dg-options "-O2 -msse2" } */ + +typedef long long __m128i __attribute__ ((__vector_size__ (16))); + +__m128i foo1(__m128i __a) +{ + return (__m128i)__builtin_ia32_pslldqi128 (__a, 8); +} + +__m128i foo2(__m128i __a) +{ + return (__m128i)__builtin_ia32_psrldqi128 (__a, 8); +} + +/* { dg-final { scan-assembler "psrldq" } } */ +/* { dg-final { scan-assembler "pslldq" } } */