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re PR target/60735 (GCC targeting E500 with SPE has errors with the _Decimal64 type)

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2014-04-02  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/60735
	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
	software floating point or no floating point registers, do not
	allow any type in the FPRs.  Eliminate a test for SPE SIMD types
	in GPRs that occurs after we tested for GPRs that would never be
	true.

	* config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
	Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
	since the FMOVE64 type is DFmode/DDmode.  If TARGET_E500_DOUBLE,
	specifically allow DDmode, since that does not use the SPE SIMD
	instructions.

From-SVN: r209025
This commit is contained in:
Michael Meissner 2014-04-02 17:03:49 +00:00 • committed by Michael Meissner
parent 7b59ff2d55
commit 690c229f46
3 changed files with 21 additions and 6 deletions
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15
gcc/ChangeLog
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@ -1,3 +1,18 @@
2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60735
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
software floating point or no floating point registers, do not
allow any type in the FPRs. Eliminate a test for SPE SIMD types
in GPRs that occurs after we tested for GPRs that would never be
true.
* config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE,
specifically allow DDmode, since that does not use the SPE SIMD
instructions.
2014-04-02 Richard Biener <rguenther@suse.de>
PR middle-end/60729

7
gcc/config/rs6000/rs6000.c
View file

@ -1752,6 +1752,9 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
modes and DImode. */
if (FP_REGNO_P (regno))
{
if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
return 0;
if (SCALAR_FLOAT_MODE_P (mode)
&& (mode != TDmode || (regno % 2) == 0)
&& FP_REGNO_P (last_regno))
@ -1780,10 +1783,6 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
|| mode == V1TImode);
/* ...but GPRs can hold SIMD data on the SPE in one register. */
if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
return 1;
/* We cannot put non-VSX TImode or PTImode anywhere except general register
and it must be able to fit within the register set. */

5
gcc/config/rs6000/rs6000.md
View file

@ -9394,8 +9394,9 @@
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
(match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
"! TARGET_POWERPC64
&& ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
|| TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
&& ((TARGET_FPRS && TARGET_DOUBLE_FLOAT)
|| TARGET_SOFT_FLOAT
|| (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"#"