[AArch64] Use atomic load-operate instructions for update-fetch patterns.
2015-09-22 Matthew Wahab <matthew.wahab@arm.com> * config/aarch64/aarch64-protos.h (aarch64_gen_atomic_ldop): Adjust declaration. * config/aarch64/aarch64.c (aarch64_emit_bic): New. (aarch64_gen_atomic_ldop): Adjust comment. Add parameter out_result. Update to support update-fetch operations. * config/aarch64/atomics.md (aarch64_atomic_exchange<mode>_lse): Adjust for change to aarch64_gen_atomic_ldop. (aarch64_atomic_<atomic_optab><mode>_lse): Likewise. (aarch64_atomic_fetch_<atomic_optab><mode>_lse): Likewise. (atomic_<atomic_optab>_fetch<mode>): Change to an expander. (aarch64_atomic_<atomic_optab>_fetch<mode>): New. (aarch64_atomic_<atomic_optab>_fetch<mode>_lse): New. gcc/testsuite 2015-09-22 Matthew Wahab <matthew.wahab@arm.com> * gcc.target/aarch64/atomic-inst-ldadd.c: Add tests for update-fetch operations. * gcc.target/aarch64/atomic-inst-ldlogic.c: Likewise. From-SVN: r228002
This commit is contained in:
Matthew Wahab
Matthew Wahab
parent
641c2f8b69
commit
68729b062d
7 changed files with 262 additions and 59 deletions
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@ -1,3 +1,18 @@
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2015-09-22 Matthew Wahab <matthew.wahab@arm.com>
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* config/aarch64/aarch64-protos.h (aarch64_gen_atomic_ldop):
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Adjust declaration.
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* config/aarch64/aarch64.c (aarch64_emit_bic): New.
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(aarch64_gen_atomic_ldop): Adjust comment. Add parameter
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out_result. Update to support update-fetch operations.
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* config/aarch64/atomics.md (aarch64_atomic_exchange<mode>_lse):
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Adjust for change to aarch64_gen_atomic_ldop.
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(aarch64_atomic_<atomic_optab><mode>_lse): Likewise.
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(aarch64_atomic_fetch_<atomic_optab><mode>_lse): Likewise.
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(atomic_<atomic_optab>_fetch<mode>): Change to an expander.
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(aarch64_atomic_<atomic_optab>_fetch<mode>): New.
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(aarch64_atomic_<atomic_optab>_fetch<mode>_lse): New.
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2015-09-22 Matthew Wahab <matthew.wahab@arm.com>
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* config/aarch64/aarch64-protos.h
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@ -380,7 +380,7 @@ void aarch64_split_compare_and_swap (rtx op[]);
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void aarch64_gen_atomic_cas (rtx, rtx, rtx, rtx, rtx);
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bool aarch64_atomic_ldop_supported_p (enum rtx_code);
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void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx);
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void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
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void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
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bool aarch64_gen_adjusted_ldpstp (rtx *, bool, enum machine_mode, RTX_CODE);
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@ -11018,6 +11018,25 @@ aarch64_split_compare_and_swap (rtx operands[])
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aarch64_emit_post_barrier (model);
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}
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/* Emit a BIC instruction. */
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static void
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aarch64_emit_bic (machine_mode mode, rtx dst, rtx s1, rtx s2, int shift)
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{
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rtx shift_rtx = GEN_INT (shift);
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rtx (*gen) (rtx, rtx, rtx, rtx);
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switch (mode)
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{
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case SImode: gen = gen_and_one_cmpl_lshrsi3; break;
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case DImode: gen = gen_and_one_cmpl_lshrdi3; break;
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default:
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gcc_unreachable ();
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}
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emit_insn (gen (dst, s2, shift_rtx, s1));
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}
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/* Emit an atomic swap. */
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static void
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@ -11112,13 +11131,14 @@ aarch64_emit_atomic_load_op (enum aarch64_atomic_load_op_code code,
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}
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/* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
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location to store the data read from memory. MEM is the memory location to
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read and modify. MODEL_RTX is the memory ordering to use. VALUE is the
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second operand for the operation. Either OUT_DATA or OUT_RESULT, but not
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both, can be NULL. */
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location to store the data read from memory. OUT_RESULT is the location to
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store the result of the operation. MEM is the memory location to read and
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modify. MODEL_RTX is the memory ordering to use. VALUE is the second
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operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
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be NULL. */
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void
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aarch64_gen_atomic_ldop (enum rtx_code code, rtx out_data,
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aarch64_gen_atomic_ldop (enum rtx_code code, rtx out_data, rtx out_result,
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rtx mem, rtx value, rtx model_rtx)
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{
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machine_mode mode = GET_MODE (mem);
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@ -11131,12 +11151,15 @@ aarch64_gen_atomic_ldop (enum rtx_code code, rtx out_data,
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if (out_data)
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out_data = gen_lowpart (mode, out_data);
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if (out_result)
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out_result = gen_lowpart (mode, out_result);
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/* Make sure the value is in a register, putting it into a destination
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register if it needs to be manipulated. */
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if (!register_operand (value, mode)
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|| code == AND || code == MINUS)
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{
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src = out_data;
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src = out_result ? out_result : out_data;
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emit_move_insn (src, gen_lowpart (mode, value));
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}
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else
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@ -11202,6 +11225,43 @@ aarch64_gen_atomic_ldop (enum rtx_code code, rtx out_data,
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}
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aarch64_emit_atomic_load_op (ldop_code, mode, out_data, src, mem, model_rtx);
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/* If necessary, calculate the data in memory after the update by redoing the
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operation from values in registers. */
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if (!out_result)
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return;
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if (short_mode)
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{
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src = gen_lowpart (wmode, src);
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out_data = gen_lowpart (wmode, out_data);
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out_result = gen_lowpart (wmode, out_result);
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}
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x = NULL_RTX;
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switch (code)
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{
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case MINUS:
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case PLUS:
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x = gen_rtx_PLUS (wmode, out_data, src);
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break;
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case IOR:
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x = gen_rtx_IOR (wmode, out_data, src);
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break;
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case XOR:
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x = gen_rtx_XOR (wmode, out_data, src);
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break;
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case AND:
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aarch64_emit_bic (wmode, out_result, out_data, src, 0);
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return;
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default:
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gcc_unreachable ();
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}
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emit_set_insn (out_result, x);
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return;
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}
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/* Split an atomic operation. */
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@ -219,7 +219,7 @@
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_gen_atomic_ldop (SET, operands[0], operands[1],
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aarch64_gen_atomic_ldop (SET, operands[0], NULL, operands[1],
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operands[2], operands[3]);
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DONE;
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}
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@ -280,7 +280,7 @@
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_gen_atomic_ldop (<CODE>, operands[3], operands[0],
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aarch64_gen_atomic_ldop (<CODE>, operands[3], NULL, operands[0],
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operands[1], operands[2]);
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DONE;
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}
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@ -368,7 +368,7 @@
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_gen_atomic_ldop (<CODE>, operands[0], operands[1],
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aarch64_gen_atomic_ldop (<CODE>, operands[0], NULL, operands[1],
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operands[2], operands[3]);
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DONE;
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}
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@ -398,7 +398,31 @@
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}
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)
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(define_insn_and_split "atomic_<atomic_optab>_fetch<mode>"
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;; Load-operate-store, returning the original memory data.
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(define_expand "atomic_<atomic_optab>_fetch<mode>"
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[(match_operand:ALLI 0 "register_operand" "")
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(atomic_op:ALLI
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "")
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(match_operand:ALLI 2 "<atomic_op_operand>" ""))
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(match_operand:SI 3 "const_int_operand")]
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""
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{
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rtx (*gen) (rtx, rtx, rtx, rtx);
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rtx value = operands[2];
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/* Use an atomic load-operate instruction when possible. */
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if (aarch64_atomic_ldop_supported_p (<CODE>))
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gen = gen_aarch64_atomic_<atomic_optab>_fetch<mode>_lse;
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else
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gen = gen_aarch64_atomic_<atomic_optab>_fetch<mode>;
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emit_insn (gen (operands[0], operands[1], value, operands[3]));
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DONE;
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})
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(define_insn_and_split "aarch64_atomic_<atomic_optab>_fetch<mode>"
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[(set (match_operand:ALLI 0 "register_operand" "=&r")
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(atomic_op:ALLI
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")
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@ -421,6 +445,29 @@
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}
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)
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(define_insn_and_split "aarch64_atomic_<atomic_optab>_fetch<mode>_lse"
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[(set (match_operand:ALLI 0 "register_operand" "=&r")
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(atomic_op:ALLI
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")
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(match_operand:ALLI 2 "<atomic_op_operand>" "r<const_atomic>")))
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(set (match_dup 1)
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(unspec_volatile:ALLI
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[(match_dup 1)
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(match_dup 2)
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(match_operand:SI 3 "const_int_operand")]
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UNSPECV_ATOMIC_LDOP))
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(clobber (match_scratch:ALLI 4 "=r"))]
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"TARGET_LSE"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_gen_atomic_ldop (<CODE>, operands[4], operands[0], operands[1],
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operands[2], operands[3]);
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DONE;
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}
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)
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(define_insn_and_split "atomic_nand_fetch<mode>"
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[(set (match_operand:ALLI 0 "register_operand" "=&r")
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(not:ALLI
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@ -1,3 +1,9 @@
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2015-09-22 Matthew Wahab <matthew.wahab@arm.com>
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* gcc.target/aarch64/atomic-inst-ldadd.c: Add tests for
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update-fetch operations.
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* gcc.target/aarch64/atomic-inst-ldlogic.c: Likewise.
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2015-09-22 Matthew Wahab <matthew.wahab@arm.com>
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* gcc.target/aarch64/atomic-inst-ldadd.c: New.
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@ -31,6 +31,29 @@
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__atomic_fetch_sub (val, foo, MODEL); \
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}
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#define ADD_LOAD(FN, TY, MODEL) \
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TY FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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return __atomic_add_fetch (val, foo, MODEL); \
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}
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#define ADD_LOAD_NORETURN(FN, TY, MODEL) \
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void FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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__atomic_add_fetch (val, foo, MODEL); \
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}
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#define SUB_LOAD(FN, TY, MODEL) \
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TY FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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return __atomic_sub_fetch (val, foo, MODEL); \
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}
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#define SUB_LOAD_NORETURN(FN, TY, MODEL) \
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void FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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__atomic_sub_fetch (val, foo, MODEL); \
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}
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TEST (load_add, LOAD_ADD)
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TEST (load_add_notreturn, LOAD_ADD_NORETURN)
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@ -38,20 +61,26 @@ TEST (load_add_notreturn, LOAD_ADD_NORETURN)
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TEST (load_sub, LOAD_SUB)
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TEST (load_sub_notreturn, LOAD_SUB_NORETURN)
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/* { dg-final { scan-assembler-times "ldaddb\t" 8} } */
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/* { dg-final { scan-assembler-times "ldaddab\t" 16} } */
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/* { dg-final { scan-assembler-times "ldaddlb\t" 8} } */
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/* { dg-final { scan-assembler-times "ldaddalb\t" 16} } */
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TEST (add_load, ADD_LOAD)
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TEST (add_load_notreturn, ADD_LOAD_NORETURN)
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/* { dg-final { scan-assembler-times "ldaddh\t" 8} } */
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/* { dg-final { scan-assembler-times "ldaddah\t" 16} } */
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/* { dg-final { scan-assembler-times "ldaddlh\t" 8} } */
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/* { dg-final { scan-assembler-times "ldaddalh\t" 16} } */
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TEST (sub_load, SUB_LOAD)
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TEST (sub_load_notreturn, SUB_LOAD_NORETURN)
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/* { dg-final { scan-assembler-times "ldadd\t" 16} } */
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/* { dg-final { scan-assembler-times "ldadda\t" 32} } */
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/* { dg-final { scan-assembler-times "ldaddl\t" 16} } */
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/* { dg-final { scan-assembler-times "ldaddal\t" 32} } */
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/* { dg-final { scan-assembler-times "ldaddb\t" 16} } */
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/* { dg-final { scan-assembler-times "ldaddab\t" 32} } */
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/* { dg-final { scan-assembler-times "ldaddlb\t" 16} } */
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/* { dg-final { scan-assembler-times "ldaddalb\t" 32} } */
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/* { dg-final { scan-assembler-times "ldaddh\t" 16} } */
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/* { dg-final { scan-assembler-times "ldaddah\t" 32} } */
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/* { dg-final { scan-assembler-times "ldaddlh\t" 16} } */
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/* { dg-final { scan-assembler-times "ldaddalh\t" 32} } */
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/* { dg-final { scan-assembler-times "ldadd\t" 32} } */
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/* { dg-final { scan-assembler-times "ldadda\t" 64} } */
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/* { dg-final { scan-assembler-times "ldaddl\t" 32} } */
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/* { dg-final { scan-assembler-times "ldaddal\t" 64} } */
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/* { dg-final { scan-assembler-not "ldaxr\t" } } */
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/* { dg-final { scan-assembler-not "stlxr\t" } } */
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@ -43,6 +43,42 @@
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__atomic_fetch_xor (val, foo, MODEL); \
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}
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#define OR_LOAD(FN, TY, MODEL) \
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TY FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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return __atomic_or_fetch (val, foo, MODEL); \
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}
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#define OR_LOAD_NORETURN(FN, TY, MODEL) \
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void FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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__atomic_or_fetch (val, foo, MODEL); \
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}
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#define AND_LOAD(FN, TY, MODEL) \
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TY FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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return __atomic_and_fetch (val, foo, MODEL); \
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}
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#define AND_LOAD_NORETURN(FN, TY, MODEL) \
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void FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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__atomic_and_fetch (val, foo, MODEL); \
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}
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#define XOR_LOAD(FN, TY, MODEL) \
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TY FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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return __atomic_xor_fetch (val, foo, MODEL); \
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}
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#define XOR_LOAD_NORETURN(FN, TY, MODEL) \
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void FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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__atomic_xor_fetch (val, foo, MODEL); \
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}
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TEST (load_or, LOAD_OR)
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TEST (load_or_notreturn, LOAD_OR_NORETURN)
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@ -53,56 +89,66 @@ TEST (load_and_notreturn, LOAD_AND_NORETURN)
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TEST (load_xor, LOAD_XOR)
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TEST (load_xor_notreturn, LOAD_XOR_NORETURN)
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TEST (or_load, OR_LOAD)
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TEST (or_load_notreturn, OR_LOAD_NORETURN)
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TEST (and_load, AND_LOAD)
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TEST (and_load_notreturn, AND_LOAD_NORETURN)
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TEST (xor_load, XOR_LOAD)
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TEST (xor_load_notreturn, XOR_LOAD_NORETURN)
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/* Load-OR. */
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/* { dg-final { scan-assembler-times "ldsetb\t" 4} } */
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/* { dg-final { scan-assembler-times "ldsetab\t" 8} } */
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/* { dg-final { scan-assembler-times "ldsetlb\t" 4} } */
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/* { dg-final { scan-assembler-times "ldsetalb\t" 8} } */
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/* { dg-final { scan-assembler-times "ldsetb\t" 8} } */
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/* { dg-final { scan-assembler-times "ldsetab\t" 16} } */
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/* { dg-final { scan-assembler-times "ldsetlb\t" 8} } */
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/* { dg-final { scan-assembler-times "ldsetalb\t" 16} } */
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/* { dg-final { scan-assembler-times "ldseth\t" 4} } */
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/* { dg-final { scan-assembler-times "ldsetah\t" 8} } */
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/* { dg-final { scan-assembler-times "ldsetlh\t" 4} } */
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/* { dg-final { scan-assembler-times "ldsetalh\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldseth\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetah\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetlh\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetalh\t" 16} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldset\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldseta\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetl\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetal\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldset\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldseta\t" 32} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetl\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetal\t" 32} } */
|
||||
|
||||
/* Load-AND. */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldclrb\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrab\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrlb\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldclralb\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrb\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrab\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrlb\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclralb\t" 16} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldclrh\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrah\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrlh\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldclralh\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrh\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrah\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrlh\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclralh\t" 16} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldclr\t" 8} */
|
||||
/* { dg-final { scan-assembler-times "ldclra\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrl\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclral\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldclr\t" 16} */
|
||||
/* { dg-final { scan-assembler-times "ldclra\t" 32} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrl\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldclral\t" 32} } */
|
||||
|
||||
/* Load-XOR. */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldeorb\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorab\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorlb\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldeoralb\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorb\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorab\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorlb\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeoralb\t" 16} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldeorh\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorah\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorlh\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldeoralh\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorh\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorah\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorlh\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeoralh\t" 16} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldeor\t" 8} */
|
||||
/* { dg-final { scan-assembler-times "ldeora\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorl\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeoral\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldeor\t" 16} */
|
||||
/* { dg-final { scan-assembler-times "ldeora\t" 32} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorl\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldeoral\t" 32} } */
|
||||
|
||||
/* { dg-final { scan-assembler-not "ldaxr\t" } } */
|
||||
/* { dg-final { scan-assembler-not "stlxr\t" } } */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue