alpha: Unify SF, DF, QI, HI, SI mode moves with enabled attribute.
For floating-point, this involves in addition conditionalizing the definition of the "f" register constraint. From-SVN: r171436
This commit is contained in:
Richard Henderson
Richard Henderson
parent
6aba5cb489
commit
67102517d5
3 changed files with 106 additions and 196 deletions
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@ -1,3 +1,16 @@
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2011-02-24 Richard Henderson <rth@redhat.com>
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* config/alpha/alpha.md (attribute isa): Add vms.
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(attribute enabled): Handle it.
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(*movsf): Merge *movsf_{nofix,fix,nofp}.
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(*movdf): Merge *movdf_{nofix,fix,nofp}.
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(*movtf): Rename from *movtf_internal for consistency.
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(*movsi): Merge with *movsi_nt_vms.
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(*movhi): Merge *movhi_nobwx, *movhi_bwx.
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(*movqi): Merge *movqi_nobwx, *movqi_bwx.
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(*mov<VEC>): Merge *mov<VEC>_fix, *mov<VEC>_nofix.
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* config/alpha/constraint.md ("f"): Use NO_REGS when fpu is disabled.
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2011-02-24 Richard Henderson <rth@redhat.com>
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* config/alpha/alpha.md (extendqihi2): Implement for BWX only.
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@ -179,7 +179,9 @@
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(const_string "false"))
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;; Used to control the "enabled" attribute on a per-instruction basis.
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(define_attr "isa" "base,bwx,max,fix,cix"
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;; For convenience, conflate ABI issues re loading of addresses with
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;; an "isa".
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(define_attr "isa" "base,bwx,max,fix,cix,vms"
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(const_string "base"))
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(define_attr "enabled" ""
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@ -187,6 +189,7 @@
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(eq_attr "isa" "max") (symbol_ref "TARGET_MAX")
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(eq_attr "isa" "fix") (symbol_ref "TARGET_FIX")
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(eq_attr "isa" "cix") (symbol_ref "TARGET_CIX")
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(eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS")
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]
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(const_int 1)))
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@ -4607,27 +4610,21 @@
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;; are done via define_expand. Start with the floating-point insns, since
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;; they are simpler.
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(define_insn "*movsf_nofix"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
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(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
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"TARGET_FPREGS && ! TARGET_FIX
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&& (register_operand (operands[0], SFmode)
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|| reg_or_0_operand (operands[1], SFmode))"
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"@
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cpys %R1,%R1,%0
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ld%, %0,%1
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bis $31,%r1,%0
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ldl %0,%1
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st%, %R1,%0
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stl %r1,%0"
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[(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
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(define_expand "movsf"
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[(set (match_operand:SF 0 "nonimmediate_operand" "")
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(match_operand:SF 1 "general_operand" ""))]
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""
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{
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if (MEM_P (operands[0])
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&& ! reg_or_0_operand (operands[1], SFmode))
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operands[1] = force_reg (SFmode, operands[1]);
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})
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(define_insn "*movsf_fix"
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(define_insn "*movsf"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
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(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
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"TARGET_FPREGS && TARGET_FIX
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&& (register_operand (operands[0], SFmode)
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|| reg_or_0_operand (operands[1], SFmode))"
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"register_operand (operands[0], SFmode)
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|| reg_or_0_operand (operands[1], SFmode)"
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"@
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cpys %R1,%R1,%0
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ld%, %0,%1
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@ -4637,41 +4634,24 @@
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stl %r1,%0
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itofs %1,%0
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ftois %1,%0"
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[(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
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[(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
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(set_attr "isa" "*,*,*,*,*,*,fix,fix")])
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(define_insn "*movsf_nofp"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
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(match_operand:SF 1 "input_operand" "rG,m,r"))]
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"! TARGET_FPREGS
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&& (register_operand (operands[0], SFmode)
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|| reg_or_0_operand (operands[1], SFmode))"
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"@
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bis $31,%r1,%0
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ldl %0,%1
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stl %r1,%0"
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[(set_attr "type" "ilog,ild,ist")])
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(define_expand "movdf"
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[(set (match_operand:DF 0 "nonimmediate_operand" "")
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(match_operand:DF 1 "general_operand" ""))]
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""
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{
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if (MEM_P (operands[0])
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&& ! reg_or_0_operand (operands[1], DFmode))
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operands[1] = force_reg (DFmode, operands[1]);
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})
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(define_insn "*movdf_nofix"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
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(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
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"TARGET_FPREGS && ! TARGET_FIX
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&& (register_operand (operands[0], DFmode)
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|| reg_or_0_operand (operands[1], DFmode))"
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"@
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cpys %R1,%R1,%0
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ld%- %0,%1
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bis $31,%r1,%0
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ldq %0,%1
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st%- %R1,%0
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stq %r1,%0"
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[(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
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(define_insn "*movdf_fix"
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(define_insn "*movdf"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
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(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
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"TARGET_FPREGS && TARGET_FIX
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&& (register_operand (operands[0], DFmode)
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|| reg_or_0_operand (operands[1], DFmode))"
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"register_operand (operands[0], DFmode)
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|| reg_or_0_operand (operands[1], DFmode)"
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"@
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cpys %R1,%R1,%0
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ld%- %0,%1
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@ -4681,24 +4661,24 @@
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stq %r1,%0
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itoft %1,%0
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ftoit %1,%0"
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[(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
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(define_insn "*movdf_nofp"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
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(match_operand:DF 1 "input_operand" "rG,m,r"))]
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"! TARGET_FPREGS
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&& (register_operand (operands[0], DFmode)
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|| reg_or_0_operand (operands[1], DFmode))"
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"@
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bis $31,%r1,%0
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ldq %0,%1
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stq %r1,%0"
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[(set_attr "type" "ilog,ild,ist")])
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[(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
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(set_attr "isa" "*,*,*,*,*,*,fix,fix")])
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;; Subregs suck for register allocation. Pretend we can move TFmode
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;; data between general registers until after reload.
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;; ??? Is this still true now that we have the lower-subreg pass?
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(define_insn_and_split "*movtf_internal"
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(define_expand "movtf"
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[(set (match_operand:TF 0 "nonimmediate_operand" "")
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(match_operand:TF 1 "general_operand" ""))]
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""
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{
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if (MEM_P (operands[0])
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&& ! reg_or_0_operand (operands[1], TFmode))
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operands[1] = force_reg (TFmode, operands[1]);
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})
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(define_insn_and_split "*movtf"
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[(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
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(match_operand:TF 1 "input_operand" "roG,rG"))]
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"register_operand (operands[0], TFmode)
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@ -4711,115 +4691,6 @@
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alpha_split_tmode_pair (operands, TFmode, true);
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})
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(define_expand "movsf"
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[(set (match_operand:SF 0 "nonimmediate_operand" "")
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(match_operand:SF 1 "general_operand" ""))]
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""
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{
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if (MEM_P (operands[0])
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&& ! reg_or_0_operand (operands[1], SFmode))
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operands[1] = force_reg (SFmode, operands[1]);
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})
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(define_expand "movdf"
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[(set (match_operand:DF 0 "nonimmediate_operand" "")
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(match_operand:DF 1 "general_operand" ""))]
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""
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{
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if (MEM_P (operands[0])
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&& ! reg_or_0_operand (operands[1], DFmode))
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operands[1] = force_reg (DFmode, operands[1]);
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})
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(define_expand "movtf"
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[(set (match_operand:TF 0 "nonimmediate_operand" "")
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(match_operand:TF 1 "general_operand" ""))]
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""
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{
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if (MEM_P (operands[0])
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&& ! reg_or_0_operand (operands[1], TFmode))
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operands[1] = force_reg (TFmode, operands[1]);
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})
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(define_insn "*movsi"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
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(match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
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"TARGET_ABI_OSF
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&& (register_operand (operands[0], SImode)
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|| reg_or_0_operand (operands[1], SImode))"
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"@
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bis $31,%r1,%0
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lda %0,%1($31)
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ldah %0,%h1($31)
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#
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ldl %0,%1
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stl %r1,%0"
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[(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
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(define_insn "*movsi_nt_vms"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
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(match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
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"TARGET_ABI_OPEN_VMS
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&& (register_operand (operands[0], SImode)
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|| reg_or_0_operand (operands[1], SImode))"
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"@
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bis $31,%1,%0
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lda %0,%1
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ldah %0,%h1
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lda %0,%1
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#
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ldl %0,%1
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stl %r1,%0"
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[(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
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(define_insn "*movhi_nobwx"
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[(set (match_operand:HI 0 "register_operand" "=r,r")
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(match_operand:HI 1 "input_operand" "rJ,n"))]
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"! TARGET_BWX
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&& (register_operand (operands[0], HImode)
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|| register_operand (operands[1], HImode))"
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"@
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bis $31,%r1,%0
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lda %0,%L1($31)"
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[(set_attr "type" "ilog,iadd")])
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(define_insn "*movhi_bwx"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
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(match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
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"TARGET_BWX
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&& (register_operand (operands[0], HImode)
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|| reg_or_0_operand (operands[1], HImode))"
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"@
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bis $31,%r1,%0
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lda %0,%L1($31)
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ldwu %0,%1
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stw %r1,%0"
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[(set_attr "type" "ilog,iadd,ild,ist")])
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(define_insn "*movqi_nobwx"
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[(set (match_operand:QI 0 "register_operand" "=r,r")
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(match_operand:QI 1 "input_operand" "rJ,n"))]
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"! TARGET_BWX
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&& (register_operand (operands[0], QImode)
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|| register_operand (operands[1], QImode))"
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"@
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bis $31,%r1,%0
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lda %0,%L1($31)"
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[(set_attr "type" "ilog,iadd")])
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(define_insn "*movqi_bwx"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
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(match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
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"TARGET_BWX
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&& (register_operand (operands[0], QImode)
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|| reg_or_0_operand (operands[1], QImode))"
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"@
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bis $31,%r1,%0
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lda %0,%L1($31)
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ldbu %0,%1
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stb %r1,%0"
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[(set_attr "type" "ilog,iadd,ild,ist")])
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;; We do two major things here: handle mem->mem and construct long
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;; constants.
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@ -4832,6 +4703,22 @@
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DONE;
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})
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(define_insn "*movsi"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r")
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(match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ,s"))]
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"register_operand (operands[0], SImode)
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|| reg_or_0_operand (operands[1], SImode)"
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"@
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bis $31,%r1,%0
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lda %0,%1($31)
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ldah %0,%h1($31)
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#
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ldl %0,%1
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stl %r1,%0
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lda %0,%1"
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[(set_attr "type" "ilog,iadd,iadd,multi,ild,ist,ldsym")
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(set_attr "isa" "*,*,*,*,*,*,vms")])
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;; Split a load of a large constant into the appropriate two-insn
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;; sequence.
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@ -5454,7 +5341,7 @@
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(match_dup 4))]
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"WORDS_BIG_ENDIAN"
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"operands[5] = force_reg (DImode, operands[0]);")
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;; Here are the define_expand's for QI and HI moves that use the above
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;; patterns. We have the normal sets, plus the ones that need scratch
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;; registers for reload.
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@ -5470,6 +5357,19 @@
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DONE;
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})
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(define_insn "*movqi"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
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(match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
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"register_operand (operands[0], QImode)
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|| reg_or_0_operand (operands[1], QImode)"
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"@
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bis $31,%r1,%0
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lda %0,%L1($31)
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ldbu %0,%1
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stb %r1,%0"
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[(set_attr "type" "ilog,iadd,ild,ist")
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(set_attr "isa" "*,*,bwx,bwx")])
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(define_expand "movhi"
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[(set (match_operand:HI 0 "nonimmediate_operand" "")
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(match_operand:HI 1 "general_operand" ""))]
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@ -5481,6 +5381,19 @@
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DONE;
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})
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(define_insn "*movhi"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
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(match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
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"register_operand (operands[0], HImode)
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|| reg_or_0_operand (operands[1], HImode)"
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"@
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bis $31,%r1,%0
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lda %0,%L1($31)
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ldwu %0,%1
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stw %r1,%0"
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[(set_attr "type" "ilog,iadd,ild,ist")
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(set_attr "isa" "*,*,bwx,bwx")])
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;; We need to hook into the extra support that we have for HImode
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;; reloads when BWX insns are not available.
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(define_expand "movcqi"
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@ -5565,7 +5478,7 @@
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[(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m")
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(match_operand:RELOAD12 1 "register_operand" "r")
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(match_operand:TI 2 "register_operand" "=&r")])]
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"! TARGET_BWX"
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"!TARGET_BWX"
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{
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unsigned regno = REGNO (operands[2]);
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@ -5676,9 +5589,8 @@
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(define_insn "*mov<mode>_fix"
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[(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
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(match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
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"TARGET_FIX
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&& (register_operand (operands[0], <MODE>mode)
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|| reg_or_0_operand (operands[1], <MODE>mode))"
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"register_operand (operands[0], <MODE>mode)
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|| reg_or_0_operand (operands[1], <MODE>mode)"
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"@
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bis $31,%r1,%0
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#
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@ -5689,23 +5601,8 @@
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stt %R1,%0
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ftoit %1,%0
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itoft %1,%0"
|
||||
[(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
|
||||
|
||||
(define_insn "*mov<mode>_nofix"
|
||||
[(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
|
||||
(match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
|
||||
"! TARGET_FIX
|
||||
&& (register_operand (operands[0], <MODE>mode)
|
||||
|| reg_or_0_operand (operands[1], <MODE>mode))"
|
||||
"@
|
||||
bis $31,%r1,%0
|
||||
#
|
||||
ldq %0,%1
|
||||
stq %r1,%0
|
||||
cpys %R1,%R1,%0
|
||||
ldt %0,%1
|
||||
stt %R1,%0"
|
||||
[(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
|
||||
[(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
|
||||
(set_attr "isa" "*,*,*,*,*,*,*,fix,fix")])
|
||||
|
||||
(define_insn "uminv8qi3"
|
||||
[(set (match_operand:V8QI 0 "register_operand" "=r")
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
(define_register_constraint "c" "R27_REG"
|
||||
"General register 27, function call address")
|
||||
|
||||
(define_register_constraint "f" "FLOAT_REGS"
|
||||
(define_register_constraint "f" "TARGET_FPREGS ? FLOAT_REGS : NO_REGS"
|
||||
"Any floating-point register")
|
||||
|
||||
(define_register_constraint "v" "R0_REG"
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue