sparc.opt (mfix-ut700): New option.
* config/sparc/sparc.opt (mfix-ut700): New option. (mfix-gr712rc): Likewise. (sparc_fix_b2bst): New variable. * doc/invoke.texi (SPARC options): Document them. (ARM options): Fix warnings. * config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP instructions to prevent sequences that can trigger the store-store errata for certain LEON3FT processors. (pass_work_around_errata::gate): Also test sparc_fix_b2bst. (sparc_option_override): Set sparc_fix_b2bst appropriately. * config/sparc/sparc.md (fix_b2bst): New attribute. (in_branch_delay): Prevent stores in delay slot if fix_b2bst. From-SVN: r250114
This commit is contained in:
Daniel Cederman
Eric Botcazou
parent
214f700a8b
commit
67091cb476
5 changed files with 133 additions and 6 deletions
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@ -1,3 +1,18 @@
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2017-07-11 Daniel Cederman <cederman@gaisler.com>
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* config/sparc/sparc.opt (mfix-ut700): New option.
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(mfix-gr712rc): Likewise.
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(sparc_fix_b2bst): New variable.
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* doc/invoke.texi (SPARC options): Document them.
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(ARM options): Fix warnings.
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* config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
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instructions to prevent sequences that can trigger the store-store
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errata for certain LEON3FT processors.
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(pass_work_around_errata::gate): Also test sparc_fix_b2bst.
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(sparc_option_override): Set sparc_fix_b2bst appropriately.
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* config/sparc/sparc.md (fix_b2bst): New attribute.
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(in_branch_delay): Prevent stores in delay slot if fix_b2bst.
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2017-07-10 Uros Bizjak <ubizjak@gmail.com>
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PR target/81375
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@ -920,6 +920,12 @@ mem_ref (rtx x)
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to properly detect the various hazards. Therefore, this machine specific
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pass runs as late as possible. */
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/* True if INSN is a md pattern or asm statement. */
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#define USEFUL_INSN_P(INSN) \
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(NONDEBUG_INSN_P (INSN) \
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&& GET_CODE (PATTERN (INSN)) != USE \
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&& GET_CODE (PATTERN (INSN)) != CLOBBER)
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static unsigned int
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sparc_do_work_around_errata (void)
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{
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@ -939,6 +945,81 @@ sparc_do_work_around_errata (void)
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if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))
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insn = seq->insn (1);
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/* Look for either of these two sequences:
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Sequence A:
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1. store of word size or less (e.g. st / stb / sth / stf)
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2. any single instruction that is not a load or store
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3. any store instruction (e.g. st / stb / sth / stf / std / stdf)
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Sequence B:
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1. store of double word size (e.g. std / stdf)
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2. any store instruction (e.g. st / stb / sth / stf / std / stdf) */
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if (sparc_fix_b2bst
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&& NONJUMP_INSN_P (insn)
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&& (set = single_set (insn)) != NULL_RTX
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&& MEM_P (SET_DEST (set)))
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{
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/* Sequence B begins with a double-word store. */
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bool seq_b = GET_MODE_SIZE (GET_MODE (SET_DEST (set))) == 8;
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rtx_insn *after;
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int i;
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next = next_active_insn (insn);
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if (!next)
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break;
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for (after = next, i = 0; i < 2; i++)
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{
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/* Skip empty assembly statements. */
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if ((GET_CODE (PATTERN (after)) == UNSPEC_VOLATILE)
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|| (USEFUL_INSN_P (after)
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&& (asm_noperands (PATTERN (after))>=0)
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&& !strcmp (decode_asm_operands (PATTERN (after),
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NULL, NULL, NULL,
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NULL, NULL), "")))
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after = next_active_insn (after);
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if (!after)
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break;
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/* If the insn is a branch, then it cannot be problematic. */
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if (!NONJUMP_INSN_P (after)
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|| GET_CODE (PATTERN (after)) == SEQUENCE)
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break;
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/* Sequence B is only two instructions long. */
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if (seq_b)
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{
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/* Add NOP if followed by a store. */
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if ((set = single_set (after)) != NULL_RTX
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&& MEM_P (SET_DEST (set)))
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insert_nop = true;
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/* Otherwise it is ok. */
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break;
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}
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/* If the second instruction is a load or a store,
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then the sequence cannot be problematic. */
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if (i == 0)
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{
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if (((set = single_set (after)) != NULL_RTX)
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&& (MEM_P (SET_DEST (set)) || MEM_P (SET_SRC (set))))
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break;
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after = next_active_insn (after);
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if (!after)
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break;
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}
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/* Add NOP if third instruction is a store. */
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if (i == 1
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&& ((set = single_set (after)) != NULL_RTX)
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&& MEM_P (SET_DEST (set)))
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insert_nop = true;
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}
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}
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else
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/* Look for a single-word load into an odd-numbered FP register. */
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if (sparc_fix_at697f
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&& NONJUMP_INSN_P (insn)
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@ -1191,8 +1272,7 @@ public:
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/* opt_pass methods: */
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virtual bool gate (function *)
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{
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/* The only errata we handle are those of the AT697F and UT699. */
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return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0;
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return sparc_fix_at697f || sparc_fix_ut699 || sparc_fix_b2bst;
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}
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virtual unsigned int execute (function *)
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@ -1557,6 +1637,10 @@ sparc_option_override (void)
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if (!(target_flags_explicit & MASK_LRA))
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target_flags |= MASK_LRA;
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/* Enable the back-to-back store errata workaround for LEON3FT. */
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if (sparc_fix_ut699 || sparc_fix_ut700 || sparc_fix_gr712rc)
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sparc_fix_b2bst = 1;
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/* Supply a default value for align_functions. */
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if (align_functions == 0)
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{
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@ -426,6 +426,10 @@
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(symbol_ref "(sparc_fix_ut699 != 0
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? FIX_UT699_TRUE : FIX_UT699_FALSE)"))
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(define_attr "fix_b2bst" "false,true"
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(symbol_ref "(sparc_fix_b2bst != 0
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? FIX_B2BST_TRUE : FIX_B2BST_FALSE)"))
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;; Length (in # of insns).
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;; Beware that setting a length greater or equal to 3 for conditional branches
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;; has a side-effect (see output_cbranch and output_v9branch).
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@ -573,6 +577,8 @@
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(define_attr "in_branch_delay" "false,true"
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(cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")
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(const_string "false")
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(and (eq_attr "fix_b2bst" "true") (eq_attr "type" "store,fpstore"))
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(const_string "false")
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(and (eq_attr "fix_ut699" "true") (eq_attr "type" "load,sload"))
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(const_string "false")
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(and (eq_attr "fix_ut699" "true")
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@ -237,6 +237,18 @@ mfix-ut699
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Target Report RejectNegative Var(sparc_fix_ut699)
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Enable workarounds for the errata of the UT699 processor.
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mfix-ut700
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Target Report RejectNegative Var(sparc_fix_ut700)
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Enable workarounds for the errata of the UT699E/UT700 processor.
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mfix-gr712rc
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Target Report RejectNegative Var(sparc_fix_gr712rc)
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Enable workarounds for the errata of the GR712RC processor.
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;; Enable workaround for back-to-back store errata
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TargetVariable
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unsigned int sparc_fix_b2bst
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Mask(LONG_DOUBLE_128)
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;; Use 128-bit long double
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@ -1128,8 +1128,8 @@ See RS/6000 and PowerPC Options.
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-mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol
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-mvis4 -mno-vis4 -mvis4b -mno-vis4b @gol
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-mcbcond -mno-cbcond -mfmaf -mno-fmaf @gol
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-mpopc -mno-popc -msubxc -mno-subxc@gol
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-mfix-at697f -mfix-ut699 @gol
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-mpopc -mno-popc -msubxc -mno-subxc @gol
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-mfix-at697f -mfix-ut699 -mfix-ut700 -mfix-gr712rc @gol
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-mlra -mno-lra}
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@emph{SPU Options}
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@ -15205,7 +15205,7 @@ default is dependent on the selected target architecture. For ARMv6
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and later architectures the default is BE8, for older architectures
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the default is BE32. BE32 format has been deprecated by ARM.
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@item -march=@var{name@r{[}+extension@dots{}@r{]}}
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@item -march=@var{name}@r{[}+extension@dots{}@r{]}
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@opindex march
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This specifies the name of the target ARM architecture. GCC uses this
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name to determine what kind of instructions it can emit when generating
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@ -15579,7 +15579,7 @@ of the build computer. At present, this feature is only supported on
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GNU/Linux, and not all architectures are recognized. If the auto-detect is
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unsuccessful the option has no effect.
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@item -mcpu=@var{name@r{[}+extension@dots{}@r{]}}
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@item -mcpu=@var{name}@r{[}+extension@dots{}@r{]}
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@opindex mcpu
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This specifies the name of the target ARM processor. GCC uses this name
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to derive the name of the target ARM architecture (as if specified
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@ -24102,6 +24102,16 @@ processor (which corresponds to erratum #13 of the AT697E processor).
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@opindex mfix-ut699
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Enable the documented workarounds for the floating-point errata and the data
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cache nullify errata of the UT699 processor.
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@item -mfix-ut700
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@opindex mfix-ut700
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Enable the documented workaround for the back-to-back store errata of
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the UT699E/UT700 processor.
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@item -mfix-gr712rc
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@opindex mfix-gr712rc
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Enable the documented workaround for the back-to-back store errata of
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the GR712RC processor.
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@end table
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These @samp{-m} options are supported in addition to the above
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