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Update loongson vector reductions.

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2015-11-06  Simon Dardis  <simon.dardis@imgtec.com>

        * config/mips/loongson.md (vec_loongson_extract_lo_<mode>): New, extract
        low part to scalar.
        (reduc_uplus_<mode>): Remove.
        (reduc_plus_scal_<mode>): Rename from reduc_splus_<mode>, Use vec
        loongson_extract_lo_<mode>.
        (reduc_smax_scal_<mode>, reduc_smin_scal_<mode>): Rename from
        reduc_smax_<mode>, reduc_smax_<mode>, use vec
        loongson_extract_lo_<mode>.
        (reduc_umax_scal_<mode>, reduc_umin_scal_<mode>): Rename.

From-SVN: r229844
This commit is contained in:
Simon Dardis 2015-11-06 11:59:20 +00:00 • committed by Simon Dardis
parent 61d371eb41
commit 66c5c67baf
2 changed files with 44 additions and 24 deletions
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12
gcc/ChangeLog
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@ -1,3 +1,15 @@
2015-11-06 Simon Dardis <simon.dardis@imgtec.com>
* config/mips/loongson.md (vec_loongson_extract_lo_<mode>): New, extract
low part to scalar.
(reduc_uplus_<mode>): Remove.
(reduc_plus_scal_<mode>): Rename from reduc_splus_<mode>, Use vec
loongson_extract_lo_<mode>.
(reduc_smax_scal_<mode>, reduc_smin_scal_<mode>): Rename from
reduc_smax_<mode>, reduc_smax_<mode>, use vec
loongson_extract_lo_<mode>.
(reduc_umax_scal_<mode>, reduc_umin_scal_<mode>): Rename.
2015-11-06 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (struct _bb_vec_info): Add region_begin/end

56
gcc/config/mips/loongson.md
View file

@ -852,58 +852,66 @@
"dsrl\t%0,%1,%2"
[(set_attr "type" "fcvt")])
(define_expand "reduc_uplus_<mode>"
[(match_operand:VWH 0 "register_operand" "")
(match_operand:VWH 1 "register_operand" "")]
(define_insn "vec_loongson_extract_lo_<mode>"
[(set (match_operand:<V_inner> 0 "register_operand" "=r")
(vec_select:<V_inner>
(match_operand:VWHB 1 "register_operand" "f")
(parallel [(const_int 0)])))]
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
{
mips_expand_vec_reduc (operands[0], operands[1], gen_add<mode>3);
DONE;
})
"mfc1\t%0,%1"
[(set_attr "type" "mfc")])
; ??? Given that we're not describing a widening reduction, we should
; not have separate optabs for signed and unsigned.
(define_expand "reduc_splus_<mode>"
[(match_operand:VWHB 0 "register_operand" "")
(define_expand "reduc_plus_scal_<mode>"
[(match_operand:<V_inner> 0 "register_operand" "")
(match_operand:VWHB 1 "register_operand" "")]
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
{
emit_insn (gen_reduc_uplus_<mode>(operands[0], operands[1]));
rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
mips_expand_vec_reduc (tmp, operands[1], gen_add<mode>3);
emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
DONE;
})
(define_expand "reduc_smax_<mode>"
[(match_operand:VWHB 0 "register_operand" "")
(define_expand "reduc_smax_scal_<mode>"
[(match_operand:<V_inner> 0 "register_operand" "")
(match_operand:VWHB 1 "register_operand" "")]
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
{
mips_expand_vec_reduc (operands[0], operands[1], gen_smax<mode>3);
rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
mips_expand_vec_reduc (tmp, operands[1], gen_smax<mode>3);
emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
DONE;
})
(define_expand "reduc_smin_<mode>"
[(match_operand:VWHB 0 "register_operand" "")
(define_expand "reduc_smin_scal_<mode>"
[(match_operand:<V_inner> 0 "register_operand" "")
(match_operand:VWHB 1 "register_operand" "")]
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
{
mips_expand_vec_reduc (operands[0], operands[1], gen_smin<mode>3);
rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
mips_expand_vec_reduc (tmp, operands[1], gen_smin<mode>3);
emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
DONE;
})
(define_expand "reduc_umax_<mode>"
[(match_operand:VB 0 "register_operand" "")
(define_expand "reduc_umax_scal_<mode>"
[(match_operand:<V_inner> 0 "register_operand" "")
(match_operand:VB 1 "register_operand" "")]
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
{
mips_expand_vec_reduc (operands[0], operands[1], gen_umax<mode>3);
rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
mips_expand_vec_reduc (tmp, operands[1], gen_umax<mode>3);
emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
DONE;
})
(define_expand "reduc_umin_<mode>"
[(match_operand:VB 0 "register_operand" "")
(define_expand "reduc_umin_scal_<mode>"
[(match_operand:<V_inner> 0 "register_operand" "")
(match_operand:VB 1 "register_operand" "")]
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
{
mips_expand_vec_reduc (operands[0], operands[1], gen_umin<mode>3);
rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
mips_expand_vec_reduc (tmp, operands[1], gen_umin<mode>3);
emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
DONE;
})