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RISC-V: Fix vwsll combine on rv32 targets

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On rv32 targets, vwsll_zext1_scalar_<mode> would trigger an ice in
maybe_legitimize_instruction when zero extending a uint32 to uint64 due
to a mismatch between the input operand's mode (DI) and the expanded insn
operand's mode (Pmode == SI). Ensure that mode of the operands match

gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Fix mode mismatch

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>
This commit is contained in:
Edwin Lu 2024-06-11 13:50:02 -07:00
parent cbf7245c8b
commit 6638ba17ea
1 changed files with 2 additions and 4 deletions
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6
gcc/config/riscv/autovec-opt.md
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@ -1517,8 +1517,7 @@
"&& 1"
[(const_int 0)]
{
if (GET_CODE (operands[2]) == SUBREG)
operands[2] = SUBREG_REG (operands[2]);
operands[2] = gen_lowpart (Pmode, operands[2]);
insn_code icode = code_for_pred_vwsll_scalar (<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
@ -1584,8 +1583,7 @@
"&& 1"
[(const_int 0)]
{
if (GET_CODE (operands[2]) == SUBREG)
operands[2] = SUBREG_REG (operands[2]);
operands[2] = gen_lowpart (Pmode, operands[2]);
insn_code icode = code_for_pred_vwsll_scalar (<V_DOUBLE_TRUNC>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;