[RS6000] lqarx and stqcx. registers
lqarx RT and stqcx. RS are valid only with even numbered gprs. The predicate to enforce this happens to allow a loophole, closed by this patch. PR target/69548 gcc/ * config/rs6000/predicates.md (quad_int_reg_operand): Don't allow subregs. gcc/testsuite/ * gcc.target/powerpc/pr69548.c: New test. From-SVN: r233065
This commit is contained in:
parent
0b256e745b
commit
65c98fdec7
4 changed files with 28 additions and 7 deletions
|
@ -1,3 +1,9 @@
|
|||
2016-02-02 Alan Modra <amodra@gmail.com>
|
||||
|
||||
PR target/69548
|
||||
* config/rs6000/predicates.md (quad_int_reg_operand): Don't
|
||||
allow subregs.
|
||||
|
||||
2016-02-02 Alan Modra <amodra@gmail.com>
|
||||
|
||||
PR target/68662
|
||||
|
|
|
@ -375,20 +375,19 @@
|
|||
|
||||
;; Return 1 if op is a general purpose register that is an even register
|
||||
;; which suitable for a load/store quad operation
|
||||
;; Subregs are not allowed here because when they are combine can
|
||||
;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
|
||||
;; think the innermost reg needs reloading, in TImode instead of
|
||||
;; PTImode. So reload will choose a reg in TImode which has no
|
||||
;; requirement that the reg be even.
|
||||
(define_predicate "quad_int_reg_operand"
|
||||
(match_operand 0 "register_operand")
|
||||
(match_code "reg")
|
||||
{
|
||||
HOST_WIDE_INT r;
|
||||
|
||||
if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
|
||||
return 0;
|
||||
|
||||
if (GET_CODE (op) == SUBREG)
|
||||
op = SUBREG_REG (op);
|
||||
|
||||
if (!REG_P (op))
|
||||
return 0;
|
||||
|
||||
r = REGNO (op);
|
||||
if (r >= FIRST_PSEUDO_REGISTER)
|
||||
return 1;
|
||||
|
|
|
@ -1,3 +1,8 @@
|
|||
2016-02-02 Alan Modra <amodra@gmail.com>
|
||||
|
||||
PR target/69548
|
||||
* gcc.target/powerpc/pr69548.c: New test.
|
||||
|
||||
2016-02-01 Jakub Jelinek <jakub@redhat.com>
|
||||
|
||||
PR rtl-optimization/69592
|
||||
|
|
11
gcc/testsuite/gcc.target/powerpc/pr69548.c
Normal file
11
gcc/testsuite/gcc.target/powerpc/pr69548.c
Normal file
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do assemble { target { powerpc*-*-* && lp64 } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-mcpu=power8 -Os -mbig" } */
|
||||
|
||||
__int128
|
||||
quad_exchange (__int128 *ptr, __int128 newval)
|
||||
{
|
||||
return __atomic_exchange_n (ptr, newval, __ATOMIC_RELAXED);
|
||||
}
|
Loading…
Add table
Reference in a new issue