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Implement __imag__ of float _Complex using shufps on x86_64.

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This patch is a follow-up improvement to my recent patch for
PR rtl-optimization/7061.  That patch added the test case
gcc.target/i386/pr7061-2.c:

float im(float _Complex a) { return __imag__ a; }

For which GCC on x86_64 currently generates:

        movq    %xmm0, %rax
        shrq    $32, %rax
        movd    %eax, %xmm0
        ret

but with this patch we now generate (the same as LLVM):

        shufps  $85, %xmm0, %xmm0
        ret

This is achieved by providing a define_insn_and_split that allows
truncated lshiftrt:DI by 32 to be performed on either SSE or general
regs, where if the register allocator prefers to use SSE, we split
to a shufps_v4si, or if not, we use a regular shrq.

2022-06-27  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
	PR rtl-optimization/7061
	* config/i386/i386.md (*highpartdisi2): New define_insn_and_split.

gcc/testsuite/ChangeLog
	PR rtl-optimization/7061
	* gcc.target/i386/pr7061-2.c: Update to look for shufps.
This commit is contained in:
Roger Sayle 2022-06-27 07:47:40 +01:00
parent f3f73e86ec
commit 64d4f27a0c
2 changed files with 29 additions and 0 deletions
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25
gcc/config/i386/i386.md
View file

@ -13249,6 +13249,31 @@
(const_string "*")))
(set_attr "mode" "<MODE>")])
;; Specialization of *lshr<mode>3_1 below, extracting the SImode
;; highpart of a DI to be extracted, but allowing it to be clobbered.
(define_insn_and_split "*highpartdisi2"
[(set (subreg:DI (match_operand:SI 0 "register_operand" "=r,x,?k") 0)
(lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0,k")
(const_int 32)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 32)))
(clobber (reg:CC FLAGS_REG))])]
{
if (SSE_REG_P (operands[0]))
{
rtx tmp = gen_rtx_REG (V4SImode, REGNO (operands[0]));
emit_insn (gen_sse_shufps_v4si (tmp, tmp, tmp,
const1_rtx, const1_rtx,
GEN_INT (5), GEN_INT (5)));
DONE;
}
operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
})
(define_insn "*lshr<mode>3_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,?k")
(lshiftrt:SWI48

4
gcc/testsuite/gcc.target/i386/pr7061-2.c
View file

@ -1,5 +1,9 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2" } */
float im(float _Complex a) { return __imag__ a; }
/* { dg-final { scan-assembler "shufps" } } */
/* { dg-final { scan-assembler-not "movd" } } */
/* { dg-final { scan-assembler-not "movq" } } */
/* { dg-final { scan-assembler-not "movss" } } */
/* { dg-final { scan-assembler-not "rsp" } } */
/* { dg-final { scan-assembler-not "shr" } } */