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gcc: xtensa: rearrange DI mode constant loading

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2020-12-16  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
gcc/
	* config/xtensa/xtensa.c (xtensa_emit_move_sequence): Try to
	replace 'l32r' with 'movi' + 'slli' when optimizing for size.
	* config/xtensa/xtensa.md (movdi): Split loading DI mode constant
	into register pair into two loads of SI mode constants.
This commit is contained in:
Takayuki 'January June' Suwa 2020-12-16 12:53:56 -08:00 • committed by Max Filippov
parent db253e8b1d
commit 64a54505ec
2 changed files with 32 additions and 2 deletions
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15
gcc/config/xtensa/xtensa.c
View file

@ -1082,6 +1082,21 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode)
if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16)
{
/* Try to emit MOVI + SLLI sequence, that is smaller
than L32R + literal. */
if (optimize_size && mode == SImode && register_operand (dst, mode))
{
HOST_WIDE_INT srcval = INTVAL (src);
int shift = ctz_hwi (srcval);
if (xtensa_simm12b (srcval >> shift))
{
emit_move_insn (dst, GEN_INT (srcval >> shift));
emit_insn (gen_ashlsi3_internal (dst, dst, GEN_INT (shift)));
return 1;
}
}
src = force_const_mem (SImode, src);
operands[1] = src;
}

19
gcc/config/xtensa/xtensa.md
View file

@ -727,8 +727,23 @@
(match_operand:DI 1 "general_operand" ""))]
""
{
if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
operands[1] = force_const_mem (DImode, operands[1]);
if (CONSTANT_P (operands[1]))
{
/* Split in halves if 64-bit Const-to-Reg moves
because of offering further optimization opportunities. */
if (register_operand (operands[0], DImode))
{
rtx first, second;
split_double (operands[1], &first, &second);
emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), first));
emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), second));
DONE;
}
if (!TARGET_CONST16)
operands[1] = force_const_mem (DImode, operands[1]);
}
if (!register_operand (operands[0], DImode)
&& !register_operand (operands[1], DImode))