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testsuite: RISC-V: Skip V and Zvbb tests for ILP32E/ILP64E ABIs

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Some tests add options for V and Zvbb extensions, but those extensions
are not compatible with the E ABI variants.  This leads to spurious test
failures when toolchain's default ABI is ILP32E or ILP64E:

  spawn ... -march=rv32ecv_zvbb ...
  cc1: error: ILP32E ABI does not support the 'D' extension
  cc1: sorry, unimplemented: Currently the 'V' implementation requires the 'M' extension

Fix by skipping the tests when toolchain's default ABI is E variant.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vandn-1.c: Skip if default
	is E ABI.
	* gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vwsll-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vwsll-template.h: Ditto.
	* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/clz-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/ctz-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/popcount-3.c: Ditto.
	* gcc.target/riscv/rvv/base/cmpmem-1.c: Ditto.
	* gcc.target/riscv/rvv/base/cmpmem-3.c: Ditto.
	* gcc.target/riscv/rvv/base/cmpmem-4.c: Ditto.
	* gcc.target/riscv/rvv/base/cpymem-1.c: Ditto.
	* gcc.target/riscv/rvv/base/cpymem-2.c: Ditto.
	* gcc.target/riscv/rvv/base/cpymem-3.c: Ditto.
	* gcc.target/riscv/rvv/base/movmem-1.c: Ditto.
	* gcc.target/riscv/rvv/base/pr115068.c: Ditto.
	* gcc.target/riscv/rvv/base/setmem-1.c: Ditto.
	* gcc.target/riscv/rvv/base/setmem-2.c: Ditto.
	* gcc.target/riscv/rvv/base/setmem-3.c: Ditto.
	* gcc.target/riscv/rvv/base/vwaddsub-1.c: Ditto.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
This commit is contained in:
Dimitar Dimitrov 2024-11-25 20:48:00 +02:00
parent 904f332cce
commit 62e7c49669
No known key found for this signature in database
GPG key ID: 963DD134E821F15D
22 changed files with 22 additions and 22 deletions
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2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-fno-vect-cost-model -fdump-tree-vect-details -mrvv-max-lmul=m4" } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
/* { dg-final { check-function-bodies "**" "" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */
/* { dg-final { check-function-bodies "**" "" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */
/* { dg-final { check-function-bodies "**" "" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-add-options riscv_v } */
/* { dg-final { check-function-bodies "**" "" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
/* { dg-add-options riscv_v } */
/* { dg-final { check-function-bodies "**" "" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
/* { dg-add-options riscv_v } */
/* { dg-final { check-function-bodies "**" "" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
/* { dg-final { check-function-bodies "**" "" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-std=gnu99" } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
/* { dg-final { check-function-bodies "**" "" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */
/* { dg-final { check-function-bodies "**" "" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */
/* { dg-final { check-function-bodies "**" "" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2" } */