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x32: Encode %esp as %rsp to avoid 0x67 prefix

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Since the upper 32 bits of stack register are always zero for x32, we
can encode %esp as %rsp to avoid 0x67 prefix in address if there is no
index or base register.

gcc/

	PR target/82267
	* config/i386/i386.c (ix86_print_operand_address_as): Encode
	%esp as %rsp to avoid 0x67 prefix if there is no index or base
	register.

gcc/testsuite/

	PR target/82267
	* gcc.target/i386/pr82267.c: New test.

From-SVN: r253127
This commit is contained in:
H.J. Lu 2017-09-24 14:37:09 -07:00
parent c6c74708b0
commit 60ba7cd38d
4 changed files with 34 additions and 0 deletions
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7
gcc/ChangeLog
View file

@ -1,3 +1,10 @@
2017-09-24 Uros Bizjak <ubizjak@gmail.com>
PR target/82267
* config/i386/i386.c (ix86_print_operand_address_as): Encode
%esp as %rsp to avoid 0x67 prefix if there is no index or base
register.
2017-09-23 Uros Bizjak <ubizjak@gmail.com>
PR bootstrap/82306

8
gcc/config/i386/i386.c
View file

@ -19953,6 +19953,14 @@ ix86_print_operand_address_as (FILE *file, rtx addr,
code = 'k';
}
/* Since the upper 32 bits of RSP are always zero for x32, we can
encode %esp as %rsp to avoid 0x67 prefix if there is no index or
base register. */
if (TARGET_X32 && Pmode == SImode
&& ((!index && base && REGNO (base) == SP_REG)
|| (!base && index && REGNO (index) == SP_REG)))
code = 'q';
if (ASSEMBLER_DIALECT == ASM_ATT)
{
if (disp)

5
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,8 @@
2017-09-24 H.J. Lu <hongjiu.lu@intel.com>
PR target/82267
* gcc.target/i386/pr82267.c: New test.
2017-09-24 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/66328

14
gcc/testsuite/gcc.target/i386/pr82267.c Normal file
View file

@ -0,0 +1,14 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-require-effective-target maybe_x32 } */
/* { dg-options "-O2 -mx32 -maddress-mode=short" } */
int
stackuse (void)
{
volatile int foo = 2;
return foo * 3;
}
/* Verify we that use %rsp to access stack. */
/* { dg-final { scan-assembler-not "%esp" } } */
/* { dg-final { scan-assembler "%rsp" } } */