x86: use VPTERNLOG for further bitwise two-vector operations
All combinations of and, ior, xor, and not involving two operands can be expressed that way in a single insn. gcc/ PR target/93768 * config/i386/i386.cc (ix86_rtx_costs): Further special-case bitwise vector operations. * config/i386/sse.md (*iornot<mode>3): New insn. (*xnor<mode>3): Likewise. (*<nlogic><mode>3): Likewise. (andor): New code iterator. (nlogic): New code attribute. (ternlog_nlogic): Likewise. gcc/testsuite/ PR target/93768 * gcc.target/i386/avx512-binop-not-1.h: New. * gcc.target/i386/avx512-binop-not-2.h: New. * gcc.target/i386/avx512f-orn-si-zmm-1.c: New test. * gcc.target/i386/avx512f-orn-si-zmm-2.c: New test.
This commit is contained in:
Jan Beulich
parent
450b9566d5
commit
607613e516
6 changed files with 198 additions and 4 deletions
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@ -21179,6 +21179,32 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
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return false;
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case IOR:
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if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
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{
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/* (ior (not ...) ...) can be a single insn in AVX512. */
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if (GET_CODE (XEXP (x, 0)) == NOT && TARGET_AVX512F
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&& (GET_MODE_SIZE (mode) == 64
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|| (TARGET_AVX512VL
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&& (GET_MODE_SIZE (mode) == 32
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|| GET_MODE_SIZE (mode) == 16))))
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{
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rtx right = GET_CODE (XEXP (x, 1)) != NOT
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? XEXP (x, 1) : XEXP (XEXP (x, 1), 0);
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*total = ix86_vec_cost (mode, cost->sse_op)
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+ rtx_cost (XEXP (XEXP (x, 0), 0), mode,
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outer_code, opno, speed)
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+ rtx_cost (right, mode, outer_code, opno, speed);
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return true;
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}
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*total = ix86_vec_cost (mode, cost->sse_op);
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}
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else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
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*total = cost->add * 2;
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else
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*total = cost->add;
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return false;
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case XOR:
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if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
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*total = ix86_vec_cost (mode, cost->sse_op);
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@ -21199,11 +21225,20 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
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/* pandn is a single instruction. */
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if (GET_CODE (XEXP (x, 0)) == NOT)
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{
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rtx right = XEXP (x, 1);
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/* (and (not ...) (not ...)) can be a single insn in AVX512. */
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if (GET_CODE (right) == NOT && TARGET_AVX512F
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&& (GET_MODE_SIZE (mode) == 64
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|| (TARGET_AVX512VL
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&& (GET_MODE_SIZE (mode) == 32
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|| GET_MODE_SIZE (mode) == 16))))
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right = XEXP (right, 0);
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*total = ix86_vec_cost (mode, cost->sse_op)
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+ rtx_cost (XEXP (XEXP (x, 0), 0), mode,
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outer_code, opno, speed)
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+ rtx_cost (XEXP (x, 1), mode,
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outer_code, opno, speed);
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+ rtx_cost (right, mode, outer_code, opno, speed);
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return true;
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}
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else if (GET_CODE (XEXP (x, 1)) == NOT)
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@ -21261,8 +21296,25 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
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case NOT:
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if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
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// vnot is pxor -1.
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*total = ix86_vec_cost (mode, cost->sse_op) + 1;
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{
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/* (not (xor ...)) can be a single insn in AVX512. */
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if (GET_CODE (XEXP (x, 0)) == XOR && TARGET_AVX512F
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&& (GET_MODE_SIZE (mode) == 64
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|| (TARGET_AVX512VL
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&& (GET_MODE_SIZE (mode) == 32
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|| GET_MODE_SIZE (mode) == 16))))
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{
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*total = ix86_vec_cost (mode, cost->sse_op)
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+ rtx_cost (XEXP (XEXP (x, 0), 0), mode,
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outer_code, opno, speed)
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+ rtx_cost (XEXP (XEXP (x, 0), 1), mode,
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outer_code, opno, speed);
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return true;
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}
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// vnot is pxor -1.
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*total = ix86_vec_cost (mode, cost->sse_op) + 1;
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}
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else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
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*total = cost->add * 2;
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else
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@ -17616,6 +17616,98 @@
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operands[2] = force_reg (V1TImode, CONSTM1_RTX (V1TImode));
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})
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(define_insn "*iornot<mode>3"
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[(set (match_operand:VI 0 "register_operand" "=v,v,v,v")
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(ior:VI
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(not:VI
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(match_operand:VI 1 "bcst_vector_operand" "v,Br,v,m"))
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(match_operand:VI 2 "bcst_vector_operand" "vBr,v,m,v")))]
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"(<MODE_SIZE> == 64 || TARGET_AVX512VL
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|| (TARGET_AVX512F && !TARGET_PREFER_AVX256))
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&& (register_operand (operands[1], <MODE>mode)
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|| register_operand (operands[2], <MODE>mode))"
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{
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if (!register_operand (operands[1], <MODE>mode))
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{
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if (TARGET_AVX512VL)
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return "vpternlog<ternlogsuffix>\t{$0xdd, %1, %2, %0|%0, %2, %1, 0xdd}";
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return "vpternlog<ternlogsuffix>\t{$0xdd, %g1, %g2, %g0|%g0, %g2, %g1, 0xdd}";
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}
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if (TARGET_AVX512VL)
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return "vpternlog<ternlogsuffix>\t{$0xbb, %2, %1, %0|%0, %1, %2, 0xbb}";
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return "vpternlog<ternlogsuffix>\t{$0xbb, %g2, %g1, %g0|%g0, %g1, %g2, 0xbb}";
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}
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[(set_attr "type" "sselog")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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(set (attr "mode")
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(if_then_else (match_test "TARGET_AVX512VL")
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(const_string "<sseinsnmode>")
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(const_string "XI")))
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(set (attr "enabled")
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(if_then_else (eq_attr "alternative" "2,3")
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(symbol_ref "<MODE_SIZE> == 64 || TARGET_AVX512VL")
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(const_string "*")))])
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(define_insn "*xnor<mode>3"
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[(set (match_operand:VI 0 "register_operand" "=v,v")
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(not:VI
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(xor:VI
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(match_operand:VI 1 "bcst_vector_operand" "%v,v")
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(match_operand:VI 2 "bcst_vector_operand" "vBr,m"))))]
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"(<MODE_SIZE> == 64 || TARGET_AVX512VL
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|| (TARGET_AVX512F && !TARGET_PREFER_AVX256))
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&& (register_operand (operands[1], <MODE>mode)
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|| register_operand (operands[2], <MODE>mode))"
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{
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if (TARGET_AVX512VL)
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return "vpternlog<ternlogsuffix>\t{$0x99, %2, %1, %0|%0, %1, %2, 0x99}";
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else
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return "vpternlog<ternlogsuffix>\t{$0x99, %g2, %g1, %g0|%g0, %g1, %g2, 0x99}";
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}
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[(set_attr "type" "sselog")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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(set (attr "mode")
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(if_then_else (match_test "TARGET_AVX512VL")
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(const_string "<sseinsnmode>")
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(const_string "XI")))
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(set (attr "enabled")
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(if_then_else (eq_attr "alternative" "1")
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(symbol_ref "<MODE_SIZE> == 64 || TARGET_AVX512VL")
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(const_string "*")))])
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(define_code_iterator andor [and ior])
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(define_code_attr nlogic [(and "nor") (ior "nand")])
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(define_code_attr ternlog_nlogic [(and "0x11") (ior "0x77")])
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(define_insn "*<nlogic><mode>3"
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[(set (match_operand:VI 0 "register_operand" "=v,v")
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(andor:VI
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(not:VI (match_operand:VI 1 "bcst_vector_operand" "%v,v"))
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(not:VI (match_operand:VI 2 "bcst_vector_operand" "vBr,m"))))]
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"(<MODE_SIZE> == 64 || TARGET_AVX512VL
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|| (TARGET_AVX512F && !TARGET_PREFER_AVX256))
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&& (register_operand (operands[1], <MODE>mode)
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|| register_operand (operands[2], <MODE>mode))"
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{
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if (TARGET_AVX512VL)
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return "vpternlog<ternlogsuffix>\t{$<ternlog_nlogic>, %2, %1, %0|%0, %1, %2, <ternlog_nlogic>}";
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else
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return "vpternlog<ternlogsuffix>\t{$<ternlog_nlogic>, %g2, %g1, %g0|%g0, %g1, %g2, <ternlog_nlogic>}";
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}
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[(set_attr "type" "sselog")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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(set (attr "mode")
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(if_then_else (match_test "TARGET_AVX512VL")
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(const_string "<sseinsnmode>")
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(const_string "XI")))
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(set (attr "enabled")
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(if_then_else (eq_attr "alternative" "1")
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(symbol_ref "<MODE_SIZE> == 64 || TARGET_AVX512VL")
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(const_string "*")))])
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(define_mode_iterator AVX512ZEXTMASK
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[(DI "TARGET_AVX512BW") (SI "TARGET_AVX512BW") HI])
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13
gcc/testsuite/gcc.target/i386/avx512-binop-not-1.h
Normal file
13
gcc/testsuite/gcc.target/i386/avx512-binop-not-1.h
Normal file
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@ -0,0 +1,13 @@
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#include <immintrin.h>
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#define PASTER2(x,y) x##y
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#define PASTER3(x,y,z) _mm##x##_##y##_##z
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#define OP(vec, op, suffix) PASTER3 (vec, op, suffix)
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#define DUP(vec, suffix, val) PASTER3 (vec, set1, suffix) (val)
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type
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foo (type x, SCALAR *f)
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{
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return OP (vec, op, suffix) (x, OP (vec, xor, suffix) (DUP (vec, suffix, *f),
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DUP (vec, suffix, ~0)));
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}
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13
gcc/testsuite/gcc.target/i386/avx512-binop-not-2.h
Normal file
13
gcc/testsuite/gcc.target/i386/avx512-binop-not-2.h
Normal file
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@ -0,0 +1,13 @@
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#include <immintrin.h>
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#define PASTER2(x,y) x##y
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#define PASTER3(x,y,z) _mm##x##_##y##_##z
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#define OP(vec, op, suffix) PASTER3 (vec, op, suffix)
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#define DUP(vec, suffix, val) PASTER3 (vec, set1, suffix) (val)
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type
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foo (type x, SCALAR *f)
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{
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return OP (vec, op, suffix) (OP (vec, xor, suffix) (x, DUP (vec, suffix, ~0)),
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DUP (vec, suffix, *f));
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}
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12
gcc/testsuite/gcc.target/i386/avx512f-orn-si-zmm-1.c
Normal file
12
gcc/testsuite/gcc.target/i386/avx512f-orn-si-zmm-1.c
Normal file
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@ -0,0 +1,12 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512f -mno-avx512vl -mprefer-vector-width=512 -O2" } */
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/* { dg-final { scan-assembler-times "vpternlogd\[ \\t\]+\\\$0xdd, \\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
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/* { dg-final { scan-assembler-not "vpbroadcast" } } */
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#define type __m512i
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#define vec 512
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#define op or
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#define suffix epi32
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#define SCALAR int
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#include "avx512-binop-not-1.h"
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12
gcc/testsuite/gcc.target/i386/avx512f-orn-si-zmm-2.c
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12
gcc/testsuite/gcc.target/i386/avx512f-orn-si-zmm-2.c
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@ -0,0 +1,12 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512f -mno-avx512vl -mprefer-vector-width=512 -O2" } */
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/* { dg-final { scan-assembler-times "vpternlogd\[ \\t\]+\\\$0xbb, \\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
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/* { dg-final { scan-assembler-not "vpbroadcast" } } */
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#define type __m512i
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#define vec 512
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#define op or
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#define suffix epi32
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#define SCALAR int
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#include "avx512-binop-not-2.h"
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