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RISC-V: Fix gather_load_run-12.c test

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FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c:
	Add vsetvli asm.
This commit is contained in:
Juzhe-Zhong 2023-08-23 10:21:22 +08:00 • committed by Pan Li
parent ea1eb12a38
commit 5f3c8075f2
1 changed files with 6 additions and 0 deletions
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6
gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c
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@ -7,6 +7,12 @@
int
main (void)
{
/* FIXME: The purpose of this assembly is to ensure that the vtype register is
initialized befor instructions such as vmv1r.v are executed. Otherwise you
will get illegal instruction errors when running with spike+pk. This is an
interim solution for reduce unnecessary failures and a unified solution
will come later. */
asm volatile("vsetivli x0, 0, e8, m1, ta, ma");
#define RUN_LOOP(DATA_TYPE, INDEX_TYPE) \
DATA_TYPE dest_##DATA_TYPE##_##INDEX_TYPE[202] = {0}; \
DATA_TYPE src_##DATA_TYPE##_##INDEX_TYPE[202] = {0}; \